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4-20
32-Bit Instructions
Branch on
Less Than
Zero Likely
BLTZL rs, offset
Branches to the target address
1
if the contents of register
rs
are less than zero. If the
conditional branch is not taken, the instruction in the branch delay slot is nullified.
Branch on
Greater
Than or
Equal to
Zero Likely
BGEZL rs, offset
Branches to the target address
1
if the contents of register
rs
are greater than or equal
to zero. If the conditional branch is not taken, the instruction in the branch delay slot is
nullified.
Branch on
Less Than
Zero and
Link Likely
BLTZALL rs, offset
Stores the address of the instruction following the delay slot into register
ra
(the Link
register). Branches to the target address
1
if the contents of register
rs
are less than
zero. If the conditional branch is not taken, the instruction in the branch delay slot is
nullified.
Branch on
Greater
Than or
Equal to
Zero and
Link Likely
BGEZALL rs, offset
Stores the address of the instruction following the delay slot into register
ra
(the Link
register). Branches to the target address
1
if the contents of register
rs
are greater than
or equal to zero. If the conditional branch is not taken, the instruction in the branch delay
slot is nullified.
Branch on
Coprocess
or z True
Likely
BCzTL offset
Computes a branch target address by adding the address of the instruction to the 16-bit
offset
(shifted left two bits and sign-extended to 32 bits). Branches to the target
address
1
(after a delay of one instruction) if Coprocessor z’s condition line
(BCPCONDPz signal) is true. If the conditional branch is not taken, the instruction in
the branch delay slot is nullified.
Branch on
Coprocess
or z False
Likely
BCzFL offset
Computes a branch target address by adding the address of the instruction to the 16-bit
offset
(shifted left two bits and sign-extended to 32 bits). Branches to the target
address
1
(after a delay of one instruction) if Coprocessor z’s condition line
(BCPCONDPz signal) is false. If the conditional branch is not taken, the instruction in
the branch delay slot is nullified.
1. All branch instruction target addresses are computed as follows: add the address of the instruction
in the delay slot and the 16-bit offset (shifted left two bits and sign-extended to 32 bits). All branches
occur after a delay of one instruction.
Table 4.14
32-Bit Branch Likely Instruction Descriptions (Cont.)
Instruction
Format and Description
(Sheet 2 of 2)