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TR4101 Exception Details and Handling
6-41
Loads the EPC register and the BD bit of the Cause register with
values as described in Section 6.3.5, “EPC Register and BD Bit
Values,” on page 6-31. These values indicate the instruction mode
and which coprocessor instruction caused the exception.
Sets the CE (coprocessor error) field of the Cause register to show
which of the four coprocessors (0, 1, 2, or 3) the TR4101 referenced
when the exception occurred. Only one unusable coprocessor can
be indicated at one time.
Servicing –
Software can identify the coprocessor unit that was
referenced by examining the contents of the Cause register CE field.
If the process is entitled to access the coprocessor, the coprocessor is
marked usable, and the corresponding user state is restored to the
coprocessor.
If the process is entitled to access the coprocessor, but the coprocessor
is known not to exist or to have failed, the system could interpret the
coprocessor instruction. If the BD bit is set in the Cause register, the
branch/jump instruction must be interpreted as described in Section
6.4.1, “Branch/Jump Instruction Emulation.” The coprocessor instruction
could then be emulated with the instruction execution restarting past the
coprocessor instruction.
If the process is not entitled to access the coprocessor, the process
executing at the time should be handed an illegal instruction/privileged
instruction fault signal. Such an error is usually fatal.
6.4.2.5 Interrupt Exception
This section describes the cause of the interrupt exception and explains
how the exception is handled and serviced.
Cause –
The interrupt exception occurs when one of eight interrupt
conditions is asserted. There are two software-generated interrupts and
six hardware-generated interrupts. The significance of these interrupts
depends on the implementation.
Each of the eight external interrupts can be individually masked by
clearing the corresponding bit in the Intr[5:0] or Sw[1:0] field of the Status
register. All eight interrupts can be masked at once by clearing the IEc
bit in the Status register.