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參數(shù)資料
| 型號： | TMS320C6727B_07 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Floating-Point Digital Signal Processors |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 98/116頁 |
| 文件大?。?/td> | 999K |
| 代理商： | TMS320C6727B_07 |
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4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog
4.16.1 RTI/Digital Watchdog Device-Specific Information
McASP0,1,2
Transmit/Receive
DMA Events
McASP0,1,2
Transmit/Receive
DMA Events
Counter 0
32-Bit + 32-Bit Prescale
(Used by DSP BIOS)
Capture 0
32-Bit + 32-Bit Prescale
Counter 1
32-Bit + 32-Bit Prescale
Capture 1
32-Bit + 32-Bit Prescale
Compare 0
32-Bit
RTI Interrupt 0
SYSCLK2
RTI Interrupt 1
Compare 1
32-Bit
RTI Interrupt 2
Compare 2
32-Bit
RTI Interrupt 3
Compare 3
32-Bit
RESET
(Internal Only)
Digital Watchdog
25-Bit Counter
Watchdog Key Register
16-Bit Key
Controlled by
CFGRTI Register
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
C672x includes an RTI timer module which is used to generate periodic interrupts. This module also
includes an optional digital watchdog feature.
Figure 4-40
contains a block diagram of the RTI module.
Figure 4-40. RTI Timer Block Diagram
The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 (but
may be started individually and may have different prescaler settings).
The counters provide the timebase against which four output comparators operate. These comparators
may be programmed to generate periodic interrupts. The comparators include an adder which
automatically updates the compare value after each periodic interrupt. This means that the DSP only
needs to initialize the comparator once with the interrupt period.
The two input captures can be triggered from any of the McASP0, McASP1, or McASP2 DMA events. The
device configuration register which selects the McASP events to measure is defined in
Table 4-39
.
Measuring the time difference between these events provides an accurate measure of the sample rates at
which the McASPs are transmitting and receiving. This measurement can be useful as a hardware assist
for a software asynchronous sample rate converter algorithm.
Peripheral and Electrical Specifications
98
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