參數(shù)資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 86/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
Table 4-29. Additional
(1)
SPI Master Timings, 4-Pin Enable Option
(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
3P + 15
0.5t
c(SPC)M
+ 3P + 15
Delay from slave assertion of
SPIx_ENA active to first
SPIx_CLK from master.
(4)
17
t
d(ENA_SPC)M
ns
3P + 15
0.5t
c(SPC)M
+ 3P + 15
0.5t
c(SPC)M
Max delay for slave to deassert
SPIx_ENA after final SPIx_CLK
edge to ensure master does not
begin the next transfer.
(5)
0
18
t
d(SPC_ENA)M
ns
0.5t
c(SPC)M
0
(1)
(2)
(3)
(4)
(5)
These parameters are in addition to the general timings for SPI master modes (
Table 4-27
).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPIx_ENA assertion.
In the case where the master SPI is ready with new data before SPIx_ENA deassertion.
Table 4-30. Additional
(1)
SPI Master Timings, 4-Pin Chip Select Option
(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
2P – 10
0.5t
c(SPC)M
+ 2P – 10
Delay from SPIx_SCS active to
first SPIx_CLK
(4)(5)
19
t
d(SCS_SPC)M
ns
2P – 10
0.5t
c(SPC)M
+ 2P – 10
0.5t
c(SPC)M
0
Delay from final SPIx_CLK edge
to master deasserting SPIx_SCS
20
t
d(SPC_SCS)M
ns
0.5t
c(SPC)M
0
(1)
(2)
(3)
(4)
(5)
(6)
These parameters are in addition to the general timings for SPI master modes (
Table 4-27
).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPIx_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7)
Peripheral and Electrical Specifications
86
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