參數(shù)資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 49/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
4.11.3 EMIF Electrical Data/Timing
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
Table 4-5
through
Table 4-10
assume testing over recommended operating conditions (see
Figure 4-7
through
Figure 4-13
).
Table 4-5. 100-MHz EMIF SDRAM Interface Timing Requirements
(1)
NO.
19
20
MIN
MAX UNIT
t
su(EM_DV-EM_CLKH)
t
h(EM_CLKH-EM_DIV)
Input setup time, read data valid on D[31:0] before EM_CLK rising
Input hold time, read data valid on D[31:0] after EM_CLK rising
3
ns
ns
1.9
(1)
For more information about supported EMIF frequency, see
Table 2-1
.
Table 4-6. 100-MHz EMIF SDRAM Interface Switching Characteristics
(1)
NO.
1
2
3
4
5
6
7
PARAMETER
MIN
10
MAX UNIT
t
c(EM_CLK)
t
w(EM_CLK)
t
d(EM_CLKH-EM_CSV)S
t
oh(EM_CLKH-EM_CSIV)S
t
d(EM_CLKH-EM_WE-DQMV)S
t
oh(EM_CLKH-EM_WE-DQMIV)S
t
d(EM_CLKH-EM_AV)S
Cycle time, EMIF clock EM_CLK
Pulse width, EMIF clock EM_CLK high or low
Delay time, EM_CLK rising to EM_CS[0] valid
Output hold time, EM_CLK rising to EM_CS[0] invalid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]
invalid
Delay time, EM_CLK rising to EM_D[31:0] valid
Output hold time, EM_CLK rising to EM_D[31:0] invalid
Delay time, EM_CLK rising to EM_RAS valid
Output hold time, EM_CLK rising to EM_RAS invalid
Delay time, EM_CLK rising to EM_CAS valid
Output hold time, EM_CLK rising to EM_CAS invalid
Delay time, EM_CLK rising to EM_WE valid
Output hold time, EM_CLK rising to EM_WE invalid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
ns
ns
ns
ns
ns
ns
ns
3
7.7
1.15
7.7
1.15
7.7
8
t
oh(EM_CLKH-EM_AIV)S
1.15
ns
9
10
11
12
13
14
15
16
17
18
t
d(EM_CLKH-EM_DV)S
t
oh(EM_CLKH-EM_DIV)S
t
d(EM_CLKH-EM_RASV)S
t
oh(EM_CLKH-EM_RASIV)S
t
d(EM_CLKH-EM_CASV)S
t
oh(EM_CLKH-EM_CASIV)S
t
d(EM_CLKH-EM_WEV)S
t
oh(EM_CLKH-EM_WEIV)S
t
dis(EM_CLKH-EM_DHZ)S
t
ena(EM_CLKH-EM_DLZ)S
7.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.15
7.7
1.15
7.7
1.15
7.7
1.15
7.7
1.15
(1)
For more information about supported EMIF frequency, see
Table 2-1
.
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Peripheral and Electrical Specifications
49
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