參數(shù)資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 84/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
4.14.3 SPI Electrical Data/Timing
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
4.14.3.1
Serial Peripheral Interface (SPI) Timing
Table 4-27
through
Table 4-34
assume testing over recommended operating conditions (see
Figure 4-33
through
Figure 4-36
).
Table 4-27. General Timing Requirements for SPIx Master Modes
(1)
NO.
MIN
MAX
UNIT
greater of 8P or
1
t
c(SPC)M
Cycle Time, SPIx_CLK, All Master Modes
256P
ns
100 ns
2
3
t
w(SPCH)M
t
w(SPCL)M
Pulse Width High, SPIx_CLK, All Master Modes
Pulse Width Low, SPIx_CLK, All Master Modes
greater of 4P or 45 ns
greater of 4P or 45 ns
ns
ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK rising
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
4P
c(SPC)M
+ 4P
Delay, initial data bit valid
on SPIx_SIMO to initial
edge on SPIx_CLK
4
t
d(SIMO_SPC)M
ns
4P
0.5t
c(SPC)M
+ 4P
15
15
Delay, subsequent bits
valid on SPIx_SIMO after
transmit edge of SPIx_CLK
5
t
d(SPC_SIMO)M
ns
15
15
0.5t
c(SPC)M
– 10
Output hold time,
SPIx_SIMO valid after
receive edge of SPIxCLK,
except for final bit
(3)
0.5t
c(SPC)M
– 10
6
t
oh(SPC_SIMO)M
ns
0.5t
c(SPC)M
– 10
0.5t
c(SPC)M
– 10
0.5P + 15
0.5P + 15
Input Setup Time,
SPIx_SOMI valid before
receive edge of SPIx_CLK
7
t
su(SOMI_SPC)M
ns
0.5P + 15
0.5P + 15
0.5P + 5
0.5P + 5
Input Hold Time,
SPIx_SOMI valid after
receive edge of SPIx_CLK
8
t
ih(SPC_SOMI)M
ns
0.5P + 5
0.5P + 5
(1)
(2)
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.
The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.
(3)
Peripheral and Electrical Specifications
84
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