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參數(shù)資料
| 型號： | TMS320C6727B_07 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Floating-Point Digital Signal Processors |
| 中文描述： | 浮點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 2/116頁 |
| 文件大?。?/td> | 999K |
| 代理商： | TMS320C6727B_07 |
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1.2 Description
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance
32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B,
TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.
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Enhanced C67x+ CPU.
The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x
DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and
floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of
2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point
instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision
floating-point, and 64-bit double-precision floating-point arithmetic.
Efficient Memory System.
The memory controller maps the large on-chip 256K-byte RAM and 384K-byte
ROM as unified program/data memory. Development is simplified since there is no fixed division between
program and data memory size as on some other devices.
The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.
Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are
supported:
Two 64-bit data accesses from the C67x+ CPU
One 256-bit program fetch from the core and program cache
One 32-bit data access from the peripheral system (either dMAX or UHPI)
The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most
program/data access conflicts to the on-chip memory. It also enables effective program execution from an
off-chip memory such as an SDRAM.
High-Performance Crossbar Switch.
A high-performance crossbar switch acts as a central hub between
the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The
crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral
connections).
Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus
masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic
fixed-priority scheme.
The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed
next by the UHPI, and finally by the CPU.
dMAX Dual Data Movement Accelerator.
The dMAX is a module designed to perform Data Movement
Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers
between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX
allows movement of data to/from any addressable memory space including internal memory, peripherals,
and external memory.
The dMAX controller includes features such as the capability to perform three-dimensional data transfers
for advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFO
with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently
processing two transfer requests (provided that they are to/from different source/destinations).
External Memory Interface (EMIF) for Flexibility and Expansion.
The external memory interface on the
C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data
width is 16 bits wide on the C6726B, C6722B, and C6720 and 32 bits wide on the C6727B.
SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.
The C6726B, C6722B, and C6720 support SDRAM devices up to 128M bits.
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Throughout the remainder of the document, TMS320C6727B (or C6727B), TMS320C6726B (or C6726B), TMS320C6722B (or C6722B),
and/or TMS320C6720 (or C6720) will be referred to as TMS320C672x (or C672x).
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 DSPs
2
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