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| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 9/73頁 |
| 文件大?。?/td> | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
17
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Input interface formats
Below figures define the input video format for each input mode, as selected by the ‘data_dman_cntl’ register
setting. Video data is always clocked in at rising edge of CLKIN. Note: for 8-bit operation with 10-bit input buses,
connect only the 8 MSB’s of each input bus used, and tie 2 LSB’s to ground.
30-bit YCbCr/RGB 4:4:4
CLKIN is equal to the 1x pixel clock.
20-bit YCbCr 4:2:2
CLKIN is equal to 1x pixel clock. The pixel clock
equals the rate of the Y input and is 2x the rate of the
2 other channels in this input format where Cb & Cr
are multiplexed onto the same input bus.
When dedicated timing is used in this mode, there is a
fixed relationship between the 1
st
active period of
HS_IN (i.e. the first CLKIN rising edge seeing HS_IN
active) and a Cb color component assumed present
during that clock period on the bus receiving CbCr
samples. When embedded timing is used in this
mode, the SAV/EAV structure also unambiguously
defines
the
CbCr
sequence,
acc.
to
SMPTE274M/296M for HDTV.
Note: figure shows the case when only 8 bits of each
10-bit input bus are used.
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