參數(shù)資料
型號： THS8210PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 60/73頁
文件大小： 2053K
代理商： THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
63
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
tst_fastramp:
DAC test control, fast
ramp
{tst_cntl2 0x1B(1)}
[0]
0 : Normal operation
1 : DAC outputs a ramp at 2x clock rate.
tst_slowramp:
DAC test control, slow
ramp
{tst_cntl2 0x1B(0)}
[0]
0 : Normal operation
1 : DAC outputs a ramp at 2X clock rate divided by
64,000. This mode has a higher priority than the one
set by tst_fastramp.
Data path control (sub-address 0x1C)
data_clk656_on:
ITU656 Output clock
control
{data_cntl 0x1C(7)}
[0]
0 : D1CLKO output off
1 : D1CLKO output on
data_fsadj:
Full-scale adjust control
{data_cntl 0x1C(6)}
[0]
Selects which full-scale setting to use. See
FSADJ<n> terminal description for nominal full-scale
adjust resistor values.
0 : Use full-scale setting from resistor connected to
FSADJ2 terminal
1 : Use full-scale setting from resistor connected to
FSADJ1 terminal
data_ifir12_bypass:
Bypass control 4:2:2 to
4:4:4
{data_cntl 0x1C(5)}
[0]
0 : interpolation filters before the CSC are in the
datapath; enabling 4:2:2 to 4:4:4 conversion
internally. This mode should be used when the input
data is in 4:2:2 format
1 : interpolation filters before the CSC are bypassed.
This mode should be used when the input data is in
4:4:4 format.
data_ifir35_bypass:
Bypass control 2x
{data_cntl 0x1C(4)}
[0]
0 : interpolation filters after the CSC are in the
datapath; enabling 1x to 2x interpolation of the video
data.
1 : interpolation filters after the CSC are bypassed.
This mode should be used when 1x DAC operation is
desired.
data_tristate656:
ITU-R BT656 output bus
{data_cntl 0x1C(3)}
[0]
0 : the ITU-R BT.656 output bus is active.
1 : the ITU-R BT656 output bus is Hi-Impedance.
data_dman_cntl(2:0): Data manager control
{data_cntl 0x1C(2:0)}
[011]
Selects the format for the input data manager, as
follows:
dman_cntl
mode
000
30-bit YCbCr/RGB 4:4:4
001
16 bit RGB 4:4:4
010
15 bit RGB 4:4:4
011
20-bit YCbCr 4:2:2
100
10-bit YCbCr 4:2:2 (ITU mode)
Others
(reserved)
Display timing generator control, part 1 (sub-
addresses 0x1D-0x3C)
dtg1_y_blank(9:0):
Y ch. blanking level
amplitude control
{dtg1_y_sync_msb 0x23(5:4) & dtg1_y_sync1_lsb
0x1D(7:0)}
[1000000000]
Sets the amplitude of the blanking level for the Y
channel.
dtg1_y_sync_low(9:0): Y ch. low sync level
amplitude control
{dtg1_y_sync_msb 0x23(3:2) & dtg1_y_sync2_lsb
0x1E(7:0)}
[0000000000]
Sets the amplitude of the negative sync and
equalization/serration/broad pulses for the Y channel.
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