參數(shù)資料
型號(hào)： THS8210PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 23/73頁
文件大?。?/td> 2053K
代理商： THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
3
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Table: Terminal description
Pin
Number
Pin Name
Type
1
Description
1
DVSS
I
Manufacturing test input. Must be tied to GND for normal
operation.
2
GND_DLL
PWR
Ground of clock doubler. Should be connected to analog
ground
3
CLKIN
I
Main
clock
input.
Video
input
data
on
the
GY[9:0]/BCb[9:0]/RCr[9:0] ports should be synchronized to
CLKIN. Depending on the input data format, CLKIN is
supplied to THS8200 at 1x or 2x of the pixel clock frequency.
4
VDD_DLL
PWR
Power supply of clock doubler, nominal 1.8V
5
I2CA
I
I2C device address LSB selection
6
PBKG
(VSS)
PWR
Substrate ground. Should be connected to analog ground.
7
FSADJ1
P
Full scale adjustment control 1. A resistor should be
connected between FSADJ1 and analog ground AGND to
control the full-scale output current of the DAC output
channels. The user can select via I2C register ‘data_fsadj’
between two
full-scale ranges, determined by FSADJ1 or
FSADJ2.
For 700mV video output (1Vpp incl sync), the nominal value is
2.94KOhm ; for 1.0Vpp video output (1.3Vpp incl. sync) output
the nominal value is 2.05 KOhm.
8
FSADJ2
P
Full scale adjustment control 2. See FSADJ1.
9
COMP2
P
Compensation pin for the internal reference amplifier. A 0.1uF
capacitor should be connected between COMP2 and analog
power supply AVDD.
10
COMP1
P
Compensation pin for the internal reference amplifier. A 0.1uF
capacitor should be connected between COMP1 and analog
power supply AVDD.
11
AVDD
PWR
Analog power supply, nominal 3.3V
12
AVSS
PWR
Analog ground
13
AGY
O
Analog output of DAC1. With the proper setting of FSADJ<n>,
this output is capable to drive 1.3V full scale into a 37.5 ohm
load
14
AVDD
PWR
Analog ground
15
ABPb
O
Analog output of DAC2. See AGY.
16
AVSS
PWR
Analog ground
17
ARPr
O
Analog output of DAC3. See AGY.
18
AVDD
PWR
Analog power supply, nominal 3.3V
19
VDD_IO
PWR
IO ring power, 1.8V or 3.3V nominal
20
GND_IO
PWR
IO ring ground
21 to 30
BCb[9:0]
I
10-bit video data input port. All 10-bits or 8 MSB bits of this
port can be connected to the video data source. In 30-bit
mode, the B data of RGB, or the Cb data of YCbCr, should be
1 I = input / O = output / B = bidirectional / PWR = power or ground / P = passive
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