- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98229 > THS8210PFP (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 22/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
29
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Display timing generator (DTG)
Overview of functionality
THS8200/10 can generate dedicated Hsync/Vsync/FieldID video synchronization outputs, as well as a composite
sync inserted on either the G/Y or all analog output channels. Both types of output synchronization can be available
simultaneously and independently programmed. Synchronization patterns are fully programmable to accommodate
all standard VESA (PC graphics) and ATSC (DTV) formats; as well as non-standard formats.
For the purpose of output video timing generation, the device is configured in HDTV, SDTV or VESA mode
(register ‘dtg1_mode’). Depending on the selected DTG mode, a number of linetypes are available to generate the
full video frame format. The timing and position of horizontal and vertical syncs, the position of horizontal and
vertical blanking intervals, and the structure, position and width of equalization pulses, pre- and post-serration
pulses within the vertical blanking interval are user-programmable.
The DTG determines:
- the frame format/field format (#pixels/line,#lines/field1,#lines/field2,#fields/frame = 1 for progressive or 2 for
interlaced formats) and its synchronization to the input data source
registers: dtg1_total_pixels,dtg1_linecnt, dtg1_frame_size, dtg1_field_size
- in slave mode, whether HS_IN,VS_IN,FID (dedicated sync inputs) are used for input video synchronization or
video timing is extracted from embedded SAV/EAV codes, as well as the relative position of the video frame with
respect to these synchronization signals
registers: dtg2_embedded_timing, dtg2_hs_in_dly, dtg2_vs_in_dly
- the I/O direction of the HS_IN,VS_IN,FID input signals (master vs. slave mode), and their polarity
registers: dtg2_hs_pol,dtg2_vs_pol,dtg2_fid_pol
- the position and width of the HS_OUT,VS_OUT output signals, and their polarity
registers: dtg2_hlength, dtg2_hdly, dtg2_vlength1, dtg2_vdly1,dtg2_vlength2,dtg2_vdly2, dtg2_vsout_pol,
dtg2_hsout_pol
- field reversal within DTG
register: dtg1_field_flip
- the active video window: width and position of horizontal blanking interval, width and position of vertical blanking
interval
registers: dtg2_bp<n>, dtg2_linetype<n> and the dtg1_spec_x registers, see below.
- the composite sync format: horizontal line timing incl. serration, interlaced sync and broad pulses on each line in
vertical blanking interval, width of vertical sync
registers: dtg1_mode, dtg1_spec_<a,b,c,d,d1,e,g,h,i,k,k1>
- the behavior of the composite sync insertion: on G/Y-channel only, or inserted on all channels, or no composite
sync insertion; the amplitudes of the inserted negative and positive sync, the amplitudes of all serration pulses and
broad pulses during the vertical blanking interval
registers: dtg1_<y,cbcr>_sync_high, dtg1_<y,cbcr>_sync_low,
- the DAC output amplitude during blanking and whether video data is passed or not during the active video portion
of lines within the vertical blanking interval that contain no vertical sync, serration or broad pulses
registers: dtg1_<y,cbcr>_blank, dtg1_pass_through
- the width of each color bar of the color bar test pattern
registers: dtg1_vesa_cbar_size
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TK10840MCBX | FM, AUDIO DEMODULATOR, PDSO20 |
| TK10840MCMG | FM, AUDIO DEMODULATOR, PDSO20 |
| TK10840MCTL | FM, AUDIO DEMODULATOR, PDSO20 |
| TK10840MCTR | FM, AUDIO DEMODULATOR, PDSO20 |
| TK10840MCTX | FM, AUDIO DEMODULATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8-38R-D | 制造商:Thomas & Betts 功能描述:HEAT SHRINK RING 8AWG 3/8 STUD 制造商:Thomas & Betts 功能描述:CATAMOUNT CABLE TIES |
| THS8-516R-D | 制造商:Thomas & Betts 功能描述:CATAMOUNT CABLE TIES |
| THS8-BS-W | 制造商:Thomas & Betts 功能描述:HEAT SHRINK BUTT SPLICE 8AWG |
| THS9 | 制造商:Apex Tool Group 功能描述:HS-9 9/32 HEX NUTDRIVER |
| THS9000 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:50 MHz to 400 MHz CASCADEABLE AMPLIFIER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。