參數(shù)資料
型號: THS8210PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 65/73頁
文件大?。?/td> 2053K
代理商: THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
68
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
1 : R/Cr data clipping at low end on
csm_bcb_high_clip_on:
B/Cb high end clipping
on/off
{csm_rcr_bcb_cntl 0x4F(1)}
[0]
0 : B/Cb data clipping at high end off
1 : B/Cb data clipping at high end on
csm_bcb_low_clip_on:B/Cb low end clipping
on/off
{csm_rcr_bcb_cntl 0x4F(0)}
[0]
0 : B/Cb data clipping at low end off
1 : B/Cb data clipping at low end on
Display timing generator control, part 2 (sub-
addresses 0x50-0x82)
dtg2_bp<n>(10:0):
breakpoint<n> line
number
{see register map table}
[00000000000]
DTG will output linetype ‘dtg2_linetype<n>’ until line#
of ‘dtg2_bp<n+1>’ is reached.
(n=1..16)
dtg2_linetype<n>(3:0): Linetype for dtg2_bp<n>
{see register map table}
[0000]
DTG will output a line format corresponding to the
table below until the next breakpoint line number is
reached.
(n=1..16)
Linetype
dtg2_linetype
<n>(3:0)
ACTIVE_VIDEO
0000
FULL_NTSP
0001
FULL_BTSP
0010
NTSP_NTSP
0011
BTSP_BTSP
0100
NTSP_BTSP
0101
BTSP_NTSP
0110
ACTIVE_NEQ
0111
NSP_ACTIVE
1000
FULL_NSP
1001
FULL_BSP
1010
FULL_NEQ
1011
NEQ_NEQ
1100
BSP_BSP
1101
BSP_NEQ
1110
NEQ_BSP
1111
dtg2_hlength(9:0):
HS_OUT width
{dtg2_hlength_lsb_hdly_msb 0x71(7:6) &
dtg2_hlength_lsb 0x70(7:0)}
[0001100000]
Sets the width of the HS_OUT output signal.
dtg2_hdly(12:0):
HS_OUT delay
{dtg2_hlength_lsb_hdly_msb 0x71(4:0) &
dtg2_hdly_lsb 0x72(7:0)}
[0000000000010]
Sets the pixel value that the HS_OUT signal is
asserted on. Note: when programmed to a value
higher than the total number of pixels per line, there
will be no HS_OUT output.
dtg2_vlength1(9:0):
VS_OUT width, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(7:6) &
dtg2_vlength1_lsb 0x73(7:0)}
[0000000011]
Sets the width of the VS_OUT output signal during
progressive scan video modes or during the vertical
blank interval of field 1 in interlaced video modes.
dtg2_vdly1(10:8):
VS_OUT delay, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(2:0) &
dtg2_vdly1_lsb 0x75(7:0)}
[00000000011]
Sets the line number that the VS_OUT signal is
asserted on for progressive video modes or for field 1
of interlaced video modes. Note: when programmed
to a value higher than the total number of lines per
frame, there will be no VS_OUT output.
dtg2_vlength2(9:0):
VS_OUT width, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(7:6) &
dtg2_vlength2_lsb 0x76(7:0)}
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