THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
55
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
I2C Register Map
R/W registers can be written and read.
R registers are read-only.
Register
Name
R/W
Sub-
address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x00
0x01
Reserved
SYSTEM
version
R
0x02
ver7
ver6
ver5
ver4
ver3
ver2
ver1
ver0
chip_ctl
R/W
0x03
vesa
_clk
dll_
bypass
vesa_
color
bars
dll_freq
_sel
dac_
pwdn
chip_
pwdn
chip_
ms
arst_
func_n
COLOR SPACE CONVERSION
csc_r11
R/W
0x04
csc_ric1(5:0)
csc_rfc1(9:8)
csc_r12
R/W
0x05
csc_rfc1(7:0)
csc_r21
R/W
0x06
csc_ric2(5:0)
csc_rfc2(9:8)
csc_r22
R/W
0x07
csc_rfc2(7:0)
csc_r31
R/W
0x08
csc_ric3(5:0)
csc_rfc3(9:8)
csc_r32
R/W
0x09
csc_rfc3(7:0)
csc_g11
R/W
0x0a
csc_gic1(5:0)
csc_gfc1(9:8)
csc_g12
R/W
0x0b
csc_gfc1(7:0)
csc_g21
R/W
0x0c
csc_gic2(5:0)
csc_gfc2(9:8)
csc_g22
RW
0x0d
csc_gfc2(7:0)
csc_g31
R/W
0x0e
csc_gic3(5:0)
csc_gfc3(9:8)
csc_g32
R/W
0x0f
csc_gfc3(7:0)
csc_b11
R/W
0x10
csc_bic1(5:0)
csc_bfc1(9:8)
csc_b12
RW
0x11
csc_bfc1(7:0)
csc_b21
R/W
0x12
csc_bic2(5:0)
csc_bfc2(9:8)
csc_b22
R/W
0x13
csc_bfc2(7:0)
csc_b31
R/W
0x14
csc_bic3(5:0)
csc_bfc3(9:8)
csc_b32
R/W
0x15
csc_bfc3(7:0)
csc_offs1
R/W
0x16
csc_offset1(9:2)
csc_
offs12
R/W
0x17
csc_offset1(1:0)
csc_offset2(9:4)
csc_
offs23
R/W
0x18
csc_offset2(3:0)
csc_offset3(9:6)
csc_offs3
R/W
0x19
csc_offset3(5:0)
csc_
bypass
Not
Used
TEST
tst_cntl1
R/W
0x1a
tst_di
gbypa
ss
tst_
offset
Reserved
tst_cntl2
R/W
0x1b
tst_ydelay(1:0)
Not
Used
Not
Used
Not
Used
Not
Used
tst_fast
ramp
tst_slo
wramp
DATAPATH
data_cntl
R/W
0x1c
data_
clk656
_on
data_fs
adj
data_ifi
r12_
bypass
data_ifi
r35_
bypass
data_tri
state65
6
data_dman_cntl(2:0)
DISPLAY TIMING GENERATION, part 1
dtg1_y_
sync1_lsb
R/W
0x1d
dtg1_y_blank(7:0)
dtg1_y_
sync2_lsb
R/W
0x1e
dtg1_y_sync_low(7:0)
dtg1_y_
sync3_lsb
R/W
0x1f
dtg1_y_sync_high(7:0)