
4-22
Registers
Offset underflow – the SYM53C710 is operating in
target mode and an ACK/ pulse is received when the
outstanding offset is zero.
Offset overflow – the other SCSI device sends a REQ/
or ACK/ pulse with data which exceeds the maximum
synchronous offset defined by the
SCSI Transfer
(SXFER)
register.
Residual data in the synchronous SCSI FIFO – a
transfer other than synchronous data receive is
started with data left in the synchronous data FIFO.
A phase change occurred with an outstanding
synchronous offset when the SYM53C710 is
operating as an initiator.
UDC
Unexpected Disconnect
This bit is only valid when the SYM53C710 is in initiator
mode. It is set when the SYM53C710 is operating in
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. When the SYM53C710
is executing SCSI SCRIPTS, an unexpected disconnect
is defined to be a disconnect that does not occur after
receiving either a Disconnect Message (0x04) or a
Command Complete Message (0x00). For example, if an
ABORT message is sent, the Target will disconnect,
resulting in a UDC. When the SYM53C710 operates in
low level mode, any disconnect can cause an interrupt,
even a valid SCSI disconnect.
2
RST/
SCSI RST/ Received
This bit is set when the SYM53C710 detects an active
RST/ signal, whether the reset is generated external to
the chip or caused by the Assert RST/ bit in the
SCSI
Control One (SCNTL1)
register. This SCSI reset
detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SCSI RST/ signal.
1
PAR
Parity Error
This bit is set when the SYM53C710 detects a parity
error while receiving or sending SCSI data. The Enable
Parity Checking bit (bit 3 in the
SCSI Control Zero
(SCNTL0)
register) must be set for this bit to become
active. A parity error occurs when receiving data from the
0