
Index
IX-3
SCID
4-10
SCNTL0
4-3
SCNTL1
4-6
SCSI bus control lines
4-17
SCSI chip ID
4-10
SCSI control one
4-6
SCSI control zero
4-3
SCSI first byte received
4-15
SCSI status one
4-23
SCSI status two
4-25
SCSI status zero
4-20
SFBR
4-15
SODR
4-23
SSTAT0
4-20
SSTAT1
4-23
SSTAT2
4-25
relative addressing
5-16
I/O instructions
5-15
reliability
1-4
reselect instruction
5-11
return instruction
5-24
S
sample interrupt service routine
2-25
SCID register
4-10
SCNTL1 register
4-6
scratch
register (SCRATCH)
4-46
SCRIPTS
interrupt instruction received (SIR)
4-49
SCRIPTS processor
2-2
features
2-2
SCSI
true end of process
4-29
SCSI bus control lines register
4-17
SCSI bus interface
2-26
differential interface
2-26
SCSI C_D/ signal bit
4-25
SCSI chip ID register
4-10
SCSI control one register
4-6
SCSI core
2-1
SCSI first byte received register
4-15
SCSI I_O/ signal bit
4-25
SCSI interface
termination
2-27
SCSI MSG/ signal bit
4-25
SCSI RST/ signal bit
4-24
SCSI status one register
4-23
SCSI status two register
4-25
SCSI status zero register
4-20
select with ATN on start sequence bit
4-5
select/reselect during selection/reselection
2-27
set instruction
5-12
,
5-14
SFBR register
4-15
signal process (SIGP)
4-28
,
4-39
single
step mode (SSM)
4-51
snoop control bit
4-35
SODR register
4-23
software reset (SRST)
4-39
stacked interrupts
2-24
start
DMA operation (STD)
4-52
start sequence bit
4-4
SYM53C700 compatibility (COM)
4-53
SYM53C710
register map
A-1
SYM53C710 testability
1-4
Symbios SCSI SCRIPTS
2-2
T
table indirect addressing
5-16
table indirect operations
I/O instructions
5-15
table relative addressing
5-17
target mode
5-11
target mode bit
4-6
,
5-7
terminator networks
SCSI termination
2-27
testing
1-4
transfer control instructions
interrupt
5-25
jump
5-23
return
5-24
W
wait reselect instruction
5-14
wait select instruction
5-12
won arbitration bit
4-24