
Interrupts
2-21
2.6 Interrupts
2.6.1 Polling vs. Hardware Interrupts
The external microprocessor can be informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used by other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the SYM53C710 asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an Interrupt
Service Routine (ISR). A hybrid approach would use hardware for long
waits, and use polling for short waits.
2.6.2 Registers
The five registers in the SYM53C710 that are used for detecting or
defining interrupts are
Interrupt Status (ISTAT)
,
SCSI Status Zero
(SSTAT0)
,
DMA Status (DSTAT)
,
SCSI Interrupt Enable (SIEN)
and
DMA
Interrupt Enable (DIEN)
.
ISTAT –
The
Interrupt Status (ISTAT)
is the only register that can be
accessed as a slave during SCRIPTS operation. Therefore, it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read after the IRQ/ pin is asserted in association
with a hardware interrupt.
If the SIP bit in the ISTAT register is set, then a SCSI-type interrupt
occurs and the
SCSI Status Zero (SSTAT0)
register should be read.
If the DIP bit in the ISTAT register is set, then a DMA-type interrupt
occurs and the
DMA Status (DSTAT)
register should be read. SCSI-type
and DMA-type interrupts may occur simultaneously, so in some cases
both SIP and DIP may be set.
SSTAT0 –
The
SCSI Status Zero (SSTAT0)
register contains the
SCSI-type interrupt bits. Reading this register determines which
condition or conditions caused the SCSI-type interrupt, and clears that
SCSI interrupt condition.