
I/O Instructions
5-15
the carry bit is set, the corresponding bit in the ALU is
set.
Clear Instruction
When the ACK/ or ATN/ bits are set, the corresponding
bits are cleared in the
SCSI Output Control Latch (SOCL)
register. ATN/ should not be cleared except for testing
purposes. When the target bit is cleared, the
corresponding bit in the
SCSI Control Zero (SCNTL0)
register is cleared. When the carry bit is cleared, the
corresponding bit in the ALU is cleared.
Relative Addressing Mode
When this bit is set, the 24-bit signed value in the
DMA
Next Data Address (DNAD)
register is used as a relative
displacement from the current DSP address.
26
This bit should only be used in conjunction with the
Select, Reselect, Wait Select, and Wait Reselect
instructions. The Select and Reselect instructions can
contain an absolute alternate jump address or a relative
transfer address.
Table Indirect Mode
When this bit is set, the 24-bit signed value in the
DMA
Byte Counter (DBC)
register is used as an offset relative
to the value in the
Data Structure Address (DSA)
register.
The SCSI ID, synchronous offset and synchronous period
are loaded from this address.
25
Prior to the start of an I/O, the DSA must be loaded with
the base address of the I/O data structure. The address
may be any longword on a longword boundary.
At the start of an I/O, the DSA is added to the 24-bit
signed offset value from the opcode to generate the
address of the required data. Both positive and negative
offsets are allowed. A subsequent fetch from the address
brings the data values into the chip.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O
operation. The I/O data structure can begin on any
longword boundary and can cross system segment
boundaries.
There are two restrictions on the placement of data in
system memory.