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| 型號： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個定時器，2個SPI，I2C和脊髓損傷接口 |
| 文件頁數(shù)： | 72/117頁 |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
4.9 RDS G.B.S
4.9.1 Introduction
The main task of the GBS module is to acquire
Group and Block Synchronization of a received
RDS data steam, which is provided in a modified
shortened cyclic code.
In order to achieve synchronization, a syndrome is
calculated on every data clock pulse. Detection of
a valid syndrome is indicated by flag VSI with as-
sociated interrupt, while the corresponding block is
kept in BL(0:2). Starting in BIT_SYNC mode the
SW can use CNA zero count interrupt (CNA=1)
and VSI check for synchronization phase. If the
synchronization criteria is fulfilled, the SW can
switch to BLK_SYNC mode, setting counter CNA
to 26 and CNB to the current block code. The SW
maintains block synchronization easily by check-
ing VSI and ORD, which indicates a correct block
order.
An optional GRP_SYNC mode can be entered for
RDS standby operation using the appropriate
counter interrupt selection.
The combination of software triggered syndrome
calculation, a second 26-bit shift register and a 26-
bit quality register, allow highly flexible error cor-
rection by software.
Single quality errors, representing a 1 or 2 bit
RDSDAT error, are indicated by the SQE flag.
They can be corrected by SW with high security.
4.9.2 Features
– Hardware implemented decoding of RDS data
stream.
– Hardware triggered syndrome calculation with
every rising edge of RDSCLK.
– Storage of 26 RDS bits (1 block).
– Fast syndrome calculation
(within 2.4
μ
s at f
OSC
=8.664MHz).
– 5-bits RDS-counter CNA and 2-bit RDS-block
counter CNB.
– Selectable counter interrupt for BIT/BLOCK/
GROUP-SYNC mode.
– “Valid Syndrome” detection unit with interrupt
and block code output.
– Selectable MMBS Radio Paging option for block
E syndrome detection.
– “Valid Block Order” flag.
– Extended “error correction by software” support.
– Software triggered syndrome calculation.
– Parallel storage of 26 RDSDAT bits and 26
QUALITY bits for high flexibility.
– Single/Multiple quality-error flags.
Figure 34. Principles of Baseband Coding
BLOCK1
BLOCK2
BLOCK3
BLOCK4
GROUP = 4 BLOCKS = 104 BITS
m
15
m
14
m
13
m
12
m
11
m
10
m
9
m
8
m
7
m
6
m
5
m
4
m
3
m
2
m
1
m
0
c
9
’
c
8
’
c
7
’
c
6
’
c
5
’
c
4
’
c
3
’
c
2
’
c
1
’
c
0
’
BLOCK = 26BITS
INFORMATION WORD =16-BITS
CHECK WORD = 10-BITS
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