參數(shù)資料
型號(hào)： ST72T85A5Q6
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口
文件頁數(shù)： 63/117頁
文件大?。?/td> 748K
代理商： ST72T85A5Q6
63/117
ST7285C
I
2
C BUS INTERFACE
(Cont’d)
Transfer sequencing:
Master transmitter: (M/SL=1)
IT1: SB =1. This interrupt is cleared by a read of SR1 followed by a write in DR.
IT2: This interrupt is cleared by a read of SR1 followed by a write in CR and in DR.
IT3: BTF=1; TRA=1. This interrupt is cleared by a read of SR1 followed by a write in DR.
Master receiver: (M/SL=1)IT4: This interrupt is cleared by a read of SR1 followed by a write in CR.
IT5: BTF=1. This interrupt is cleared by a read of SR1 followed by a read of DR.
Slave transmitter: (M/SL=0)
IT6: ADSL =1. This interrupt is cleared by a read of SR1 followed by a write in DR.
IT7: BTF=1, TRA=1. This interrupt is cleared by a read of SR1 followed by a write in DR.
IT8: StopF=1. This interrupt is cleared by a read of SR2.
Slave receiver: (M/SL=0)
IT9: ADSL =1. This interrupt is cleared by a read of SR1.
IT10: BTF=1. This interrupt is cleared by a read of SR1 followed by a read of DR.
10 bits addressing (Master):
Master:
IT11: ADD10=1. This interrupt is cleared by a read of SR1 followed by a write in DR.
Slave:
During IT1,2,3,4,5,6,7,9,10,11 the SCL line is hold low.
S: Start; P: Stop; A: Acknowledge; IT: interrupt.
Detailed timing information is available in the ELECTRICAL CHARACTERISTICS.
S
IT1
ADD
A
IT2
IT3
DATA
A
IT3
DATA
A
IT3
P
S
IT1
ADD
A
IT4
DATA
A
IT5
DATA
A
IT5
P
S
ADD
A
IT6
IT7
DATA
A
IT7
DATA
A
IT7
P
IT8
S
ADD
A
IT9
DATA
A
IT10
DATA
A
IT10
P
IT8
S
ADD
A
IT11
ADD
A
IT2
S
ADD
A
ADD
A
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