- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385871 > ST72T85A5Q6 (意法半導(dǎo)體) 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES PDF資料下載
參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 69/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)當(dāng)前第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
69/117
ST7285C
RDS DEMODULATOR
(Cont’d)
4.8.2 Functional Description
The RDS Demodulator is fed with a 57KHz band-
pass filtered and limited multiplex signal.
It contains the following functional blocks:
–
57kHz PL
L. This circuit is implemented as a var-
iable counter controlled by a “COSTAS” phase
comparator. To achieve fast lockup time, thelow-
pass filter features four software selectable time
constants. Following a reset, the longest time
constant is selected and used for the locked con-
dition. The time constant relates to the time
needed to compensate a 90 degree phase devi-
ation. As the PLL locks to 0 and 180 degrees,
whatever is closest, this is the maximum possible
phase deviation. The selectable time constants
are listed in the following register description.
–
1187.5Hz PLL
. This circuit detects zero cross-
ings of the phase of the input signal. After low
pass filtering, this information is used to control a
variable divider, which generates the RDS clock.
The timeconstant of the low pass filter is also se-
lectable in four steps.
The regulation of both PLLs may be inhibited by
software. This may be used to “freeze” the actual
phase relation in order to bridge a certain time of
weak or non-existing input signal. (e.g. during AF
tests, breakdown in field strength,...). Depending
of the precision of the quartz oscillator some sec-
onds of weak input signal may be spanned with-
out loosing the lock condition.
–
“Polarity” Phase Decoder
. With the help o the
recovered 57kHz carrier, the sign of theinput sig-
nal phase is integrated over one bit (48 sam-
ples).
–
“Integral” Phase Decoder
. The relative phase
angle of the input signal to the recovered carrier
is measured. Again 48 samples are accumulat-
ed. Regarding of the “polarity phase decoder,
this system is less sensitive to the precision of
the recovered carrier, but is more sensitive with
respect to ignition spikes.
–
Differential Decoder
. Every phase decoder out-
put is fed into itsown differential decoder. For er-
ror correction purposes, a quality bit can be
generated in order to mark all differences be-
tween the two decoder outputs.
–
QualityDetector
.Thisunitmeasures theamount
of opposite phase samples. With anerror freesig-
nal; every bit consists of 24 positive and 24 neg-
ative phase samples related to the carrier. Dueto
noise, this balance may be disturbed. all bits with
a relation greater than 40 to 8 are marked as bad.
This quality information may be used by the soft-
ware foran improved error correction. Italso may
be used internally (selection by software) to
switch automatically between “polarity” and “inte-
gral” phase decoders.
The source of RDS data may be one or the other
output of these two decoders.
The source of the quality output may be selected
from the quality detector or from the exor which
builds the difference between the two differential
decoders.
–
ARI Indicator
. In order to receive a correct RDS
signal,the57KHzPLLregulation mustbechanged
inaccordance withthepresence ofARI.Therefore
a fast ARI indicator is implemented. This function
may be optionally taken over by software.
–
Interface Registers
. These allow control of the
Demodulator circuit by the MCU. Register de-
scriptions are given below:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST730C08L3 | PHASE CONTROL THYRISTORS |
| ST730C08L3L | PHASE CONTROL THYRISTORS |
| ST730C12L0 | PHASE CONTROL THYRISTORS |
| ST730C12L0L | PHASE CONTROL THYRISTORS |
| ST730C12L1 | PHASE CONTROL THYRISTORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST730 | 制造商:IRF 制造商全稱:International Rectifier 功能描述:PHASE CONTROL THYRISTORS Hockey Puk Version |
| ST7-30 | 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST-7300 | 制造商:GC Electronics 功能描述: |
| ST730186-3 | 制造商:KEMET Corporation 功能描述: 制造商:KET 功能描述: |
| ST730268-1 | 制造商:KEMET Corporation 功能描述: 制造商:KET 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。