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| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 22/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
3.6 POWER SAVING MODES
3.6.1 Slow Mode
The following Power Saving mode may be select-
ed by setting the relevant bits in the Miscellaneous
register as detailed in Section3.2.
In Slow Mode, the oscillator frequency can be di-
vided by 4, 8, 16 or 32 rather than by 2. The CPU
and peripherals are clocked at this lower frequen-
cy, and therefore the RDS filter cannot operate
correctly in this mode. SLOW mode is used to re-
duce power consumption, and enables the user to
adapt clock frequency to available supply voltage.
Figure 11. Wait Mode Flow Chart
3.6.2 Wait Mode
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During WAIT mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers
and memory remain un-
changed. The MCU will remain in WAIT mode until
an Interrupt or Reset occurs, whereupon the Pro-
gram Counter branches to the starting address of
the Interrupt or Reset Service Routine.
Refer to Figure 11 below.
WAIT
Y
VR02062D
N
Y
Y
N
EXTERNAL
INTERRUPT
RESET
RESTART
PROCESSORCLOCK
FETCHRESET
VECTOROR
SERVICEINTERRUPT
PERIPHERAL
INTERRUPT
N
ACTIVE OSCILLATOR
AND PERIPHERALS
CLOCKS ACTIVE
PROCESSORCLOCK
STOPPED
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