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參數(shù)資料
| 型號： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個定時器，2個SPI，I2C和脊髓損傷接口 |
| 文件頁數(shù)： | 18/117頁 |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
3.3 RESETS
3.3.1 Introduction
There are four sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.3.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low to reset the whole application.
3.3.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The RESET pin may thus be
used to ensure V
DD
has risen to a point where the
MCU can operate correctly before the User pro-
gram is run. Following a Reset event, or after exit-
Figure 9. Reset Block Diagram
ing Halt mode, a 4096 CPU Clock cycle delay pe-
riod is initiated in order to allow the oscillator to
stabilise and to ensure that recovery has taken
place from the Reset state.
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low for 3 machine cy-
cles (6 oscillator cycles). In its high state, an inter-
nal pull-up resistor of about 300K
is connected to
the Reset pin. This resistor can be pulled low by
external circuitry to reset the device.
3.3.4 Power-on Reset
This circuit detects the ramping up of V
DD
, and
generates a pulse thatis used to reset the applica-
tion (at approximately V
DD
= 2V).
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
Caution
: to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external pulse
may be required to correctly reactivate the circuit.
VDD
C
RESET
to ST7
VR2062C
300K
WATCHDOG RESET
OR DLPSS
RESET
OSCILLATOR
SIGNAL
INTERNAL
RESET
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