參數(shù)資料
型號(hào): SMC032BFY6E
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50
封裝: LEAD FREE, CARD-50
文件頁數(shù): 9/90頁
文件大?。?/td> 1863K
代理商: SMC032BFY6E
SMCxxxBF
Electrical interface
D15-D00
(PC card memory mode)
I/O
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
23,22,21
Carry the data, commands and status information between
the host and the controller. D00 is the LSB of the even byte
of the word. D08 is the LSB of the odd byte of the word.
D15-D00
(PC card I/O mode)
Same as PC card memory mode.
D15-D00
(True IDE mode)
All task file operations occur in byte mode on D00 to D07
while all data transfers are 16 bits using D00 to D15.
GND
(PC card memory mode)
1,50
Ground.
GND
(PC card I/O mode)
Same for all modes.
GND
(True IDE mode)
Same for all modes.
INPACK
(PC card memory mode)
O43
Not used, should not be connected to the host.
INPACK
(PC card I/O mode)
The input acknowledge is asserted when the card is
selected and responding to an I/O read cycle at the current
address on the bus. It is used by the host to control the
enable of any input data buffers between the card and CPU.
DMARQ
(True IDE mode)
The DMARQ input signal is used to request a DMA data
transfer between the host and the card. It is asserted to
notify that the card is ready to transfer data to or from the
host. For multi-word DMA transfers, the direction of data
transfer is controlled by -IORD and -IOWR.
DMARQ is used in conjunction with –DMACK to perform
handshaking: the card waits until –DMACK has been
asserted by the host to de-assert DMARQ, and re-assert it
again if there is still data to be transferred (see
DMARQ is not driven when the card is not selected.
If the host does not support DMA mode, DMARQ should be
left unconnected.
IORD
(PC card memory mode)
I34
Not used.
IORD
(PC card I/O mode)
I/O read strobe generated by the host. It gates I/O data onto
the bus.
IORD
(True IDE mode)
Same as PC card I/O mode.
Table 9.
Signal descriptions (continued)
Signal name
Dir.
Pin
Description
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