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參數(shù)資料
| 型號(hào)： | SMC032BFY6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50 |
| 封裝： | LEAD FREE, CARD-50 |
| 文件頁(yè)數(shù)： | 38/90頁(yè) |
| 文件大小： | 1863K |
| 代理商： | SMC032BFY6E |
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SMCxxxBF
Software interface
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd
addresses between 400h and 7FFh access register 9. This 1-Kbyte memory window to the
data register is provided so that hosts can perform memory-to-memory block moves to the
data register when the register lies in memory space. Some hosts, such as the X86
processors, must increment both the source and destination addresses when executing the
memory-to-memory block move instruction. Some PCMCIA socket adapters also have an
embedded auto incrementing address logic.
A word access to address at offset 8 will provide even data on the least significant byte of
the data bus, along with odd data at offset 9 on the most significant byte of the data bus.
Table 37.
Memory mapped decoding
–
REG A10
A9 to
A4
A3 A2 A1 A0 Offset
–
OE=0
–
WE=0
1
0
X
0000
0h
Even data register
1
0
X
0001
1h
Error register
Feature register
1
0
X
0010
2h
Sector count register
1
0
X
0011
3h
Sector number
register
Sector number register
1
0
X
0100
4h
Cylinder low register
1
0
X
0101
5h
Cylinder high register
1
0
X
0110
6h
Select card/head
register
Select card/head register
1
0
X
0111
7h
Status register
Command register
1
0
X
1000
8h
Dup. even data
register
Dup. even data register
1
0
X
1001
9h
Dup. odd data
register
Dup. odd data register
1
0
X
1101
Dh
Dup. error register
Dup. feature register
1
0
X
1110
Eh
Alternate status
register
Device control register
1
0
X
1111
Fh
Drive address register
Reserved
1
X
0
8h
Even data register
1
X
1
9h
Odd data register
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