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參數(shù)資料
| 型號： | SMC032BFY6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50 |
| 封裝： | LEAD FREE, CARD-50 |
| 文件頁數(shù)： | 47/90頁 |
| 文件大?。?/td> | 1863K |
| 代理商： | SMC032BFY6E |
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SMCxxxBF
CF-ATA registers
9.9
Status & alternate status registers
The status & alternate status registers are located at addresses 1F7h [177h] and 3F6h
[376h], respectively. Offsets are 7h and Eh.
These registers return the card status when read by the host.
Reading the status register clears a pending interrupt. Reading the auxiliary status register
does not clear a pending interrupt.
The status register should be accessed in byte mode; in word mode it is recommended that
alternate status register is used. The status bits are described as follows.
9.9.1
Bit 7 (BUSY)
The busy bit is set when only the card can access the command register and buffer, The
host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
9.9.2
Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash memory card
operations. This bit is cleared at power up and remains cleared until the card is ready to
accept a command.
9.9.3
Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
9.9.4
Bit 4 (DSC)
This bit is set when the card is ready.
9.9.5
Bit 3 (DRQ)
The data request is set when the card requires information be transferred either to or from
the host through the data register. The bit is cleared by the next command.
9.9.6
Bit 2 (CORR)
This bit is set when a correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
9.9.7
Bit 1 (IDX)
This bit is always set to ‘0’.
Table 44.
Drive/head register
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
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