參數(shù)資料
型號: SMC032BFY6E
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50
封裝: LEAD FREE, CARD-50
文件頁數(shù): 42/90頁
文件大小: 1863K
代理商: SMC032BFY6E
SMCxxxBF
CF-ATA registers
9
CF-ATA registers
The following section describes the hardware registers used by the host software to issue
commands to the card. These registers are collectively referred to as the ‘task file’.
In accordance with the PCMCIA specification, each register that is located at an odd offset
address can be accessed in the PC card memory or PC card I/O modes. The register can
be addressed in two ways:
Using the normal register address
Using the corresponding even address (normal address -1) when -CE1 is High and -
CE2 Low, unless -IOIS16 is High (not asserted by the card) and an I/O cycle is in
progress. Register data are input or output on data bus lines D15-D8.
In true IDE mode, the size of the transfer is based solely on the register being addressed. All
registers are 8-bit only except for the data register, which is normally 16 bits. However, they
can be configured to be accessed in 8-bit mode for non-DMA operations, by using a Set
Features command (see Section 10.17).
9.1
Data register
The data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.
The data register is a 16-bit register used to transfer data blocks between the card data
buffer and the host. This register overlaps the error register. Table 41 and Table 42
describes the combinations of data register access and explains the overlapped data and
error/feature registers. Because of the overlapped registers, access to the 1F1h, 171h or
offset 1 are not defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as
accesses to the word data register. The duplicated registers at offsets 8, 9 and Dh have no
restrictions on the operations that can be performed.
Table 41.
Data register access (memory and I/O mode)
Data register
–CE2
–CE1
A0
-REG(1)
Offset
Data bus
Word data register
0
X
-
0h, 8h, 9h
D15 to D0
Even data register
1
0
-
0h, 8h
D7 to D0
Odd data register
1
0
1
-
9h
D7 to D0
Odd data register
0
1
X
-
8h, 9h
D15 to D8
Error/feature register
1
0
1
-
1h, Dh
D7 to D0
Error/feature register
0
1
X
-
1h
D15 to D8
Error/feature register
0
X
-
Dh
D15 to D8
1.
-REG signal is mode dependent. It must be Low when the card operates in I/O mode and High when it operates in memory
mode.
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