參數(shù)資料
型號: SMC032BFY6E
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50
封裝: LEAD FREE, CARD-50
文件頁數(shù): 10/90頁
文件大小: 1863K
代理商: SMC032BFY6E
Electrical interface
SMCxxxBF
CD1, –CD2
(PC card memory mode)
O
26,25
These are connected to ground on the card. They are used
by the host to determine that the card is fully inserted into its
socket.
CD1, –CD2
(PC card I/O mode)
Same for all modes.
CD1, –CD2
(True IDE mode)
Same for all modes.
CE1, –CE2
(PC card memory mode)
I7,32
Used to select the card and to indicate whether a byte or a
word operation is being performed. –CE2 accesses the odd
Byte, –CE1 accesses the even byte or the odd byte
depending on A0 and –CE2. A multiplexing scheme based
on A0, –CE1, –CE2 allows 8-bit hosts to access all data on
D0 to D7.
CE1, –CE2
(PC card I/O mode)
Same as PC card memory mode.
CS0, –CS1
(True IDE mode)
CS0 is the chip select for the task file registers, while –CS1
selects the alternate status register and the device control
register.
When –DMACK is asserted, -CS0 and –CS1 must be de-
asserted and data width is 16 bits.
CSEL
(PC card memory mode)
Not used.
CSEL
(PC card I/O mode)
I
39
Not used.
CSEL
(True IDE mode)
This internally pulled up signal is used to configure the card
as a master or slave. When grounded it is configured as a
master, when open it is configured as a slave.
IOWR
(PC card memory mode)
I35
Not used.
IOWR
(PC card I/O mode)
The I/O write strobe pulse is used to clock I/O data on the
bus into the card controller registers. Clocking occurs on the
rising edge.
IOWR
(True IDE mode)
Same as PC card I/O mode.
OE
(PC card memory mode)
I9
This is an Output Enable strobe generated by the host
interface. It reads data and the CIS and configuration
registers.
OE
(PC card I/O mode)
Reads the CIS and configuration registers.
ATASEL
(True IDE mode)
This input signal must be driven Low to enable true IDE
mode.
Table 9.
Signal descriptions (continued)
Signal name
Dir.
Pin
Description
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