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參數(shù)資料
| 型號： | SMC032BFY6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50 |
| 封裝： | LEAD FREE, CARD-50 |
| 文件頁數(shù)： | 40/90頁 |
| 文件大?。?/td> | 1863K |
| 代理商： | SMC032BFY6E |
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SMCxxxBF
Software interface
8.4
I/O primary and secondary address configurations
When the system decodes the primary and secondary address configurations, the registers
are accessed in the block of I/O space as shown in Table 39.
As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 don’t care) as a word register on the combined odd and even data bus (D15 to
D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte
accesses to offset 0. The address space of this word register overlaps the address space of
the error and feature byte-wide registers at offset 1. When accessed twice as byte register
with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A
byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature
(write) register.
Table 39.
Primary and secondary I/O decoding
–
REG
A9 to
A4
A3
A2
A1
A0
–
IORD=0
–
IOWR=0
0
1F(17)h
0
Even data register
0
1F(17)h
0
1
Error register
Feature register
0
1F(17)h
0
1
0
Sector count register
0
1F(17)h
0
1
Sector number register
0
1F(17)h
0
1
0
Cylinder low register
0
1F(17)h
0
1
0
1
Cylinder high register
0
1F(17)h
0
1
0
Select card/head register
0
1F(17)h
0
1
Status register
Command register
0
3F(37)h
0
1
0
Alternate status register
Device control register
0
3F(37)h
0
1
Drive address register
Reserved
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SMC04-5-L | 制造商:ELDECO 制造商全稱:ELDECO 功能描述:Standard : UL - IEC 300V - 320V 15A - 17.5A |
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