參數(shù)資料
型號: SMC032BFY6E
廠商: NUMONYX
元件分類: PROM
英文描述: 4M X 8 FLASH 3.3V PROM CARD, 300 ns, UUC50
封裝: LEAD FREE, CARD-50
文件頁數(shù): 24/90頁
文件大小: 1863K
代理商: SMC032BFY6E
Command interface
SMCxxxBF
Table 22.
True IDE PIO mode read/write timing (1)
Symbol
Parameter
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Unit
t0
(2)
Cycle time (min)
600
383
240
180
120
100
80
ns
t1
Address Valid to -IORD/-IOWR
setup (min)
70
50
30
25
15
10
ns
t2
-IORD/-IOWR (min)
165
125
100
80
70
65
55
ns
t2
-IORD/-IOWR (min) register (8
bit)
290
80
70
65
55
ns
t2i
-IORD/-IOWR recovery time
(min)
-
7025
2520
ns
t3
-IOWR data setup (min)
60
45
30
20
15
ns
t4
-IOWR data hold (min)
30
20
15
10
5
ns
t5
-IORD data setup (min)
50
35
20
15
10
ns
t6
-IORD data hold (min)
5
ns
t6Z
(3)
-IORD data tri-state (max)
30
20
ns
t7
(4)
Address valid to -IOCS16
assertion (max)
90
50
40
NA
ns
t8
Address valid to -IOCS16
released (max)
60
45
30
NA
ns
t9
-IORD/-IOWR to address valid
hold
20
15
10
ns
1.
The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load.
2.
t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time
or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual
command inactive time. The three timing requirements of t0, t2, and t2i have to be met. The minimum total cycle time
requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to
ensure that t0 is equal to or greater than the value reported in the device's identify drive data. A CompactFlash memory card
implementation should support any legal host implementation.
3.
This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by the
CompactFlash memory card (tri-state).
4.
t7 and t8 apply only to modes 0, 1 and 2. The -IOCS16 signal is not valid for other modes.
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