參數(shù)資料
型號(hào): SCANPSC100F
廠商: Fairchild Semiconductor Corporation
英文描述: Embedded Boundary Scan Controller (IEEE 1149.1 Support)
中文描述: 嵌入式邊界掃描控制器協(xié)會(huì)(IEEE 1149.1支援)
文件頁(yè)數(shù): 6/21頁(yè)
文件大?。?/td> 208K
代理商: SCANPSC100F
www.fairchildsemi.com
6
S
Parallel Processor Interface (PPI)
(Continued)
TIMING WAVEFORMS
FIGURE 2. Write Cycle
FIGURE 3. Read Cycle
Note 1:
Valid data is provided on the RDY line a t
PD1
after R/W is asserted LOW or a t
PD2
after valid data is decoded on A2:0. The RDY line will remain HIGH
until the addressed register is ready to participate in the write operation. This condition only applies when writing to a shifter/buffer and is eliminated (i.e.,
RDY will go LOW immediately once valid) when using shifter/buffer status polling (discussed later in this datasheet).
Note 2:
Valid data will not appear on D7:0 (and RDY will remain HIGH) until the addressed register is ready to participate in the read operation. When the
addressed register becomes ready (i.e., a byte is available to be read), valid data will be placed on the D7:0 bus and the RDY pin will go LOW allowing the
bus cycle to continue. This read cycle delay only applies when reading the TDI shifter/buffer and is eliminated when using shifter/buffer status poling.
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