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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller (IEEE 1149.1 Support) |
| 中文描述： | 嵌入式邊界掃描控制器協(xié)會（IEEE 1149.1支援） |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100F |
www.fairchildsemi.com
20
S
AC Electrical Characteristics/Operating Requirements
(Continued)
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 10:
SSC Mode
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Typ
12.0
14.0
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
19.5
18.5
Units
Figure
(V)
Number
(Note 9)
5.0
Min
19.5
18.5
Max
Max
t
W
Clock Pulse Width
SCK (L)
SCK (H)
ns
Figures 4, 6
t
W1
Pulse Width
STB (H or L)
Maximum
5.0
5.5
2.0
5.5
ns
Figures 4, 6
f
MAX
5.0
25
35
25
MHz
Frequency Clock
SERIAL SCAN INTERFACE (SSI)
t
PD5
Prop Delay
SCK to TCK
t
PD6
Prop Delay
SCK to TDO
5.0
3.0
8.0
11.0
3.0
12.0
ns
Figure 15
5.0
5.5
12.0
16.0
5.5
17.5
ns
Figure 15
t
PD7
Prop Delay
SCK to TMS
Prop Delay
5.0
4.5
11.0
14.5
4.5
15.5
ns
Figure 15
t
PD8
5.0
3.0
8.0
10.5
3.0
11.5
ns
Figure 15
FRZ to TCK
Enable Time
OE to JTAG
t
EN4
5.0
2.0
7.0
10.0
2.0
11.0
ns
Figure 14
t
DIS4
Disable Time
OE to JTAG
Hold Time, H or L
5.0
1.0
6.0
9.0
1.0
10.0
ns
Figure 14
t
H5
5.0
0.5
1.5
2.0
3.0
3.5
0.5
ns
Figure 15
TDI to SCK (Note 10)
Setup Time, H or L
TDI to SCK (Note 10)
0.0
5.0
6.5
0.0
5.0
6.5
Figure 15
Figure 15
Figure 15
t
S5
5.0
ns
RST RELATED TIMING
t
PD
Prop Delay
RST to D
5.0
8.0
17.5
24.0
8.0
25.5
ns
t
PD
Prop Delay
RST to RDY
Prop Delay
5.0
8.0
19.5
25.5
8.0
28.0
ns
t
PHL
5.0
7.0
16.5
24.5
7.0
24.5
ns
RST to INT
Prop Delay
RST to TDO
t
PLH
5.0
5.5
12.5
17.0
5.5
18.5
ns
t
PLH
Prop Delay
RST to TMS
Pulse Width
5.0
5.5
12.0
16.0
5.5
17.5
ns
t
WR
5.0
6.0
4.0
6.0
ns
RST (L)
Recovery Time
SCK from RST
t
REC
5.0
1.0
0.5
1.0
ns
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