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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller (IEEE 1149.1 Support) |
| 中文描述： | 嵌入式邊界掃描控制器協(xié)會（IEEE 1149.1支援） |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100F |
19
www.fairchildsemi.com
S
DC Electrical Characteristics
(Continued)
Note 8:
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
AC Electrical Characteristics/Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
Typ
T
A
=
40
°
C to
+
85
°
C
Guaranteed Limits
Units
Conditions
I
CCMAX
Maximum Quiescent
Supply Current
Maximum
5.5
768
840
μ
A
TDI, OE LOW
I
CCT
5.5
0.6
1.50
mA
V
IN
=
V
CC
2.1V
Float: TDI, OE
V
IN
=
V
CC
2.1V
TDI and OE Only
I
CC
/Input
Maximum
I
CC
/Input
I
CCTR
5.5
0.65
1.65
mA
Float Untested Pin
V
IH
=
V
CC
, V
IL
=
0,
V
CC
=
Max, Outputs Open,
F
SCK
=
25 MHz
I
CCD
Dynamic Power
Supply Current
mA/
MHz
5.5
1.70
2.30
2.30
(Note 8)
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Typ
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
Units
Figure
(V)
Number
(Note 9)
Min
Max
Max
PARALLEL PROCESSOR INTERFACE (PPI)
t
PD1
Prop Delay
R/W to RDY
5.0
5.0
14.0
19.5
5.0
24.0
ns
Figures 2, 3,
4
t
PD2
Prop Delay
A to RDY
Prop Delay
5.0
5.0
14.0
19.5
5.0
24.0
ns
Figures 2, 3
t
PD3
5.0
5.0
14.0
19.5
5.0
24.0
ns
Figure 3
A to D
Prop Delay
STB to RDY
t
PD4
5.0
8.0
14.5
19.0
8.0
20.5
ns
Figures 2, 3,
4, 6
t
EN1
Enable Time
CE to RDY
Disable Time
5.0
2.0
7.0
10.0
2.0
11.0
ns
Figures 2, 3
t
DIS1
5.0
1.0
5.5
8.0
1.0
9.0
ns
Figures 2, 3
CE to RDY
Enable Time
CE to D
t
EN2
5.0
3.0
9.5
13.5
3.0
14.5
ns
Figure 3
t
DIS2
Disable Time
CE to D
Enable Time
5.0
2.5
7.5
11.0
2.5
12.0
ns
Figure 3
t
EN3
5.0
3.0
10.0
14.0
3.0
15.0
ns
Figure 3
R/W to D
Disable Time
R/W to D
t
DIS3
5.0
3.0
8.5
12.5
3.0
13.5
ns
Figure 3
t
H1
Hold Time,
R/W to STB
Setup Time
5.0
0.5
0.0
0.5
ns
Figures 2, 3,
4, 6
t
S1
5.0
1.0
0.0
1.0
ns
Figures 2, 3,
4, 6
R/W to STB
Hold Time,
A to STB
↑
Setup Time,
A to STB
↑
Hold Time,
D to STB
↑
Setup Time,
D to STB
↑
Setup Time,
STB
↑
to SCK
↓
t
H2
5.0
4.0
2.5
4.0
ns
Figures 2, 3
t
S2
5.0
4.0
1.5
4.0
ns
Figures 2, 3
t
H3
5.0
4.0
2.5
4.0
ns
Figure 2
t
S3
5.0
0.0
2.0
0.0
ns
Figure 2
t
S4
5.0
7.0
5.0
7.0
ns
Figures 4, 5,
6, 7
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