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參數(shù)資料
| 型號(hào)： | SCANPSC100F |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller (IEEE 1149.1 Support) |
| 中文描述： | 嵌入式邊界掃描控制器協(xié)會(huì)（IEEE 1149.1支援） |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100F |
www.fairchildsemi.com
4
S
Mode and Status Registers
MODE REGISTER 0 (MODE0)
This register is purely a mode register. All bits are writable
and readable. The value 00100000 is placed in this register
upon RST low or a synchronous reset operation.
Bit 7:
This bit enables the TDO shifter/buffer for shift
operations. If this bit is set, the TDO shifter/
buffer will cause TCK to stop if it is empty.
This bit enables the TDI shifter/buffer for shift
operations. If this bit is set, the TDI shifter/
buffer will cause TCK to stop if it is full.
This bit enables the 32-bit counter. If this bit is
set, the counter will cause TCK to stop if has
not been loaded or if it has reached terminal
count.
Bit 6:
Bit 5:
Bit 4:
This bit enables the TMS0 shifter/buffer for
shift operations. If this bit is set, the TMS0
shifter/buffer will cause TCK to stop if it is
empty.
This bit enables the TMS1 shifter/buffer for
shift operations. If this bit is set, the TMS1
shifter/buffer will cause TCK to stop if it is
empty.
This bit is reserved and should remain as a
logic 0 during all 'PSC100 operations.
If this bit is set, TMS will be forced high when
the 32-bit counter is at state (00000001)h.
This bit causes TDI to be connected directly
back through TDO for Loop-Around opera-
tions.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
MODE REGISTER 1 (MODE1)
This register is purely a mode register. All bits are writable
and readable. The value 00000000 is placed in this register
upon RST low or a synchronous reset operation.
Bit 7:
If this bit is set and the TDO shifter/buffer is
not full (i.e., one or both 8-bit TDO FIFOs are
empty), the INT pin will go HIGH.
Bit 6:
If this bit is set and the TDI shifter/buffer is not
empty (i.e., one or both 8-bit TDI FIFOs are
full), the INT pin will go HIGH.
Bit 5:
If this bit is set, and the 32-bit counter is not
loaded or has reached terminal count, the INT
pin will go HIGH.
Bit 4:
This bit signifies that the TD0 shifter/buffer is
reconfigured as a 32-Bit Pseudo Random Pat-
tern Generator. If set, and MODE0 Bit 7 is set,
the TDO shifter/buffer will stop TCK until a
seed value has been written to all four of the
8-bit LFSR segments.
Bit 3:
This bit signifies that the TD1 shifter/buffer is
reconfigured as a 16-Bit Serial Signature
Compactor. If set, and MODE0 Bit 6 is set, the
TDI shifter/buffer will cause TCK to stop until
a seed value has been written to the two TDI
registers.
Bit 2:
If this bit is set, a high value on FRZ will force
TCK high (see TCK Control Section).
Bits 1 and 0: These bits are used to control Test Loop-
Back operations according to the following
table.
Bit 7
TDO
Enable
Bit 6
TDI
Enable
Bit 5
CNT32
Enable
Bit 4
TMS0
Enable
Bit 3
TMS1
Enable
Bit 2
Bit 1
Bit 0
Auto TMS High
Enable
Loop-Around
Enable
Reserved
Bit 7
TDO
Interrupt
Enable
Bit 6
TDI
Interrupt
Enable
Bit 5
CNT32
Interrupt
Enable
Bit 4
PRPG
Enable
Bit 3
SSC
Enable
Bit 2
Freeze
Pin
Enable
Bit 1
Test
Loop-
Back
Bit 0
Test
Loop-
Back
MODE1
Bit 1
0
0
1
1
MODE1
Bit 0
0
1
0
1
Function
Normal Operation
Loop-Back TDO to TDI
Loop-Back TMS0 to TDI
Loop Back TMS1 to TDI
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