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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller (IEEE 1149.1 Support) |
| 中文描述： | 嵌入式邊界掃描控制器協(xié)會（IEEE 1149.1支援） |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100F |
www.fairchildsemi.com
12
S
Serial Scan Interface (SSI)
(Continued)
FIGURE 11. TDO Shifter/Buffer Block Diagram Register Hookup
FIGURE 12. TDO PRPG Block Diagram
The PRPG is loaded by four PPI writes to the TDO
address. When the PRPG enable bit is set, a pulse is
issued internally that initializes the local parallel load logic
such that the PRPG is loaded sequentially, least significant
byte first, most significant byte last. When in PRPG mode,
writes can be completed at any time; however, shift opera-
tions will be disabled until the PRPG is fully loaded.
LOOP AROUND MODE
. This mode, enabled by setting bit
0 in Mode Register 0, will cause data appearing at the TDI
input to be placed directly back on the TDO output. This
feature can be used for read-only scan operations where
data is shifted into TDI while returning the scan chain to its
previous state when shifting is completed. It can also be
used to bypass PSC100 devices connected within a
boundary scan chain (i.e., a PSC100 located within a
chain, but not providing the JTAG TAP data). Loop around
has limited usefulness in most boundary scan applications
since, typically, data in the scan chain is shifted out and
evaluated as new data is shifted into the chain for the next
test.
WRITING A PARTIAL BYTE TO THE TMS0, TMS1 OR
TDO SHIFTER/BUFFER.
Since the TMS0, TMS1 and TDO
shifter/buffers shift out least significant bit first, the valid
(meaningful) bits within a partial byte (i.e., byte containing
<
8 valid bits to be shifted to the scan chain) must be stored
and written into the shifter/buffer as the least significant
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