參數(shù)資料
型號(hào): SC16C554B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大),16字節(jié)的FIFO
文件頁數(shù): 37/51頁
文件大?。?/td> 253K
代理商: SC16C554B
9397 750 13133
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 9 February 2005
37 of 51
Philips Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency =
[3]
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
10.1 Timing diagrams
t
28d
delay from start to reset
TXRDY
address setup time
chip select strobe width
address hold time
read cycle delay
delay from CS to data
data disable time
write strobe setup time
write strobe hold time
write cycle delay
data setup time
data hold time
RESET pulse width
baud rate divisor
-
8 T
RCLK
[3]
-
8 T
RCLK
[3]
-
8 T
RCLK
[3]
ns
t
30s
t
30w
t
30h
t
30d
t
31d
t
31h
t
32s
t
32h
t
32d
t
33s
t
33h
t
RESET
N
10
-
-
-
-
90
15
-
-
-
-
-
-
2
16
1
T
RCLK
[3]
10
26
15
20
-
-
10
10
25
15
5
40
1 T
RCLK
[3]
-
-
-
-
26
15
-
-
-
-
-
-
2
16
1
T
RCLK
[3]
10
23
15
20
-
-
10
10
20
15
5
40
1 T
RCLK
[3]
-
-
-
-
23
15
-
-
-
-
-
-
2
16
1
T
RCLK
[3]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25 pF load
[1]
90
15
20
-
-
10
10
25
20
15
200
1 T
RCLK
[3]
25 pF load
25 pF load
25 pF load
Table 26:
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V 3.3 V or 5.0 V
±
10 %, unless otherwise specified.
Symbol Parameter
Conditions
Dynamic characteristics
…continued
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
3w
-------
Fig 14. General read timing in 68 mode
002aaa210
t
30s
A0 to A4
CS
R/W
D0 to D7
t
30w
t
30h
t
30d
t
31h
t
32s
t
31d
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