參數(shù)資料
型號: S29NS512PABBJW003
廠商: SPANSION LLC
元件分類: DRAM
英文描述: MirrorBit Flash Family
中文描述: 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝: 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁數(shù): 67/86頁
文件大?。?/td> 2234K
代理商: S29NS512PABBJW003
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
67
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 10.5
V
CC
Power-Up Diagram
10.7
CLK Characterization
Figure 10.6
CLK Characterization
10.8
AC Characteristics
10.8.1
Synchronous/Burst Read
V
CC
RESET#
t
VCS
t
RH
CE#
V
CC min
V
IH
Table 10.4
CLK Characterization
Parameter
Description
66 MHz
83 MHz
108 MHz
Unit
f
CLK
CLK Frequency
Max
66
83
108
MHz
Min
60 KHz in 8 word Burst,
120 KHz in 16 word Burst,
250 KHz in 32 word Burst,
1 MHz in Continuous Mode
t
CLK
CLK Period
Min
15.1
12.5
9.26
ns
t
CL
/t
CH
CLK Low/High Time
Min
0.40 t
CLK
ns
Max
0.60 t
CLK
t
CR
CLK Rise Time
Max
3.0
2.5
1.5
ns
t
CF
CLK Fall Time
t
CLK
t
CL
t
CH
t
CR
t
CF
CLK
Table 10.5
Synchronous/Burst Read
Parameter
Description
66 MHz
83 MHz
108 MHz
Unit
JEDEC
Standard
t
IACC
Synchronous Access Time
Max
80
ns
t
BACC
Burst Access Time Valid Clock to Output Delay
Max
11.2
9
7.6
ns
t
ACS
Address Setup Time to CLK
(1)
Min
4
ns
t
ACH
Address Hold Time from CLK
(1)
Min
6
5
5
ns
t
BDH
Data Hold Time
Min
3
3
2
ns
t
RDY
Chip Enable to RDY Active
Max
10
ns
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