參數(shù)資料
型號： S29NS512PABBJW003
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MirrorBit Flash Family
中文描述： 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁數(shù)： 5/86頁
文件大?。?/td> 2234K
代理商： S29NS512PABBJW003
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
5
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figures
Figure 3.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 7.1
Figure 7.2
Figure 7.3
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 10.11 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 10.12 Asynchronous Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 10.13 Chip/Sector Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 10.14 Accelerated Unlock Bypass Programming Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 10.15 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 10.16 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.18 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.19 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.20 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 10.21 Back-to-Back Read/Write Cycle Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10
44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11
44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11
VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P. . . . . . . . . . . . . . . . . . 12
VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13
Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Advanced Sector Protection/Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
V
CC
Power-Up Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8-Word Linear Synchronous Single Data Rate Burst with Wrap Around. . . . . . . . . . . . . . . . 68
8-Word Linear Single Data Read Synchronous Burst without Wrap Around. . . . . . . . . . . . . 69
Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
相關(guān)PDF資料
PDF描述
S29NS-P MirrorBit Flash Family
S29PL127N65GFWW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL127N 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65GAWW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65GAWW03 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS-J 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
S29NS-J_07 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
S29NS-N 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS-N_07 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS-P 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
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