參數(shù)資料
型號： S29NS512PABBJW003
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MirrorBit Flash Family
中文描述： 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁數(shù)： 33/86頁
文件大?。?/td> 2234K
代理商： S29NS512PABBJW003
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
33
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Notes
1. The addresses are latched by rising edge of CLK.
2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default).
3. A software reset command is required after read command.
4. CR0.3 is ignored if in continuous read mode (no wrap around).
6.4
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This
mode is primarily intended for programming equipment to automatically match a device with its corresponding
programming algorithm. The Autoselect codes can also be accessed in the system. When verifying sector
protection, the sector address must appear on the appropriate highest order address bits (see
Table 6.12
).
The remaining address bits are don't care. The most significant four bits of the address during the third write
cycle select the bank from which the Autoselect codes are read by the host. All other banks can be accessed
normally for data read without exiting the Autoselect mode.
CR1.0
Programmable
Wait State
(Note 1)
0000
=
initial data is
valid on the
2nd
rising
CLK edge
AVD# transition
to V
IH
0001
3rd
CR0.13
0010
4th
0011
5th
CR0.12
0100
6th
0101
7th
CR0.11
0110
=
Reserved
0111
1000
=
initial data is
valid on the
8th
rising
CLK edge
AVD# transition
to V
IH
1001
9th
…
1101
=
initial data is
valid on the
13th
rising
CLK edge
AVD# transition
to V
IH
(Default)
1110
=
Reserved
1111
CR0.10
RDY
Polarity
0 = RDY signal is active low
1 = RDY signal is active high (Default)
CR0.9
Reserved
(Not used)
0 = Reserved
1 = Reserved (Default)
CR0.8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (Default)
CR0.7
Reserved
(Not used)
0 = Reserved
1 = Reserved (Default)
CR0.6
Reserved
(Not used)
0 = Reserved
1 = Reserved (Default)
CR0.5
Reserved
(Not used)
0 = Reserved (Default)
1 = Reserved
CR1.4
Output Drive
Strength
0 = Full Drive= Current Driver Strength (Default)
1 = Half Drive
CR0.4
RDY Function
0 = RDY (Default)
1 = Reserved
CR0.3
Burst Wrap
Around
0 = No Wrap Around Burst
1 = Wrap Around Burst (Default)
CR0.2
Burst
Length
000 = Continuous (Default)
010 = 8-Word Linear Burst
CR0.1
011 = 16-Word Linear Burst
CR0.0
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Table 6.11
Configuration Register
CR Bit
Function
Settings (Binary)
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PDF描述
S29NS-P MirrorBit Flash Family
S29PL127N65GFWW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
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