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Publication Number
S29NS-P_00
Revision
A
Amendment
1
Issue Date
February 20, 2007
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit Technology
Multiplexed Data and Address for reduced I/O count
Simultaneous Read/Write operation
Full/Half drive output slew rate control
32-word Write Buffer
Sixteen-bank architecture consisting of
64/32/16 MB for NS512/256/128P, respectively
Four 32 KB sectors at the top of memory array (NS256/128P)
512 128KB sectors (NS512P), 255/127 128KB sectors (NS256/
128P)
Programmable linear (8/16/32) with or without wrap around
and continuous burst read modes
Secured Silicon Sector region consisting of 128 words each
for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of highest two sectors
Top Boot sector configuration (NS256/128P)
Handshaking by monitoring RDY
Offered Packages
– NS512P: 64-ball FBGA (8 mm x 9.2 mm)
– NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm)
Low V
CC
write inhibit
Persistent and Password methods of Advanced Sector
Protection
Write operation status bits indicate program and erase
operation completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming
time
Synchronous or Asynchronous program operation,
independent of burst control register settings
V
PP
input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Performance Characteristics
General Description
The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
multiplexed data and address pins. These products can operate up to 108 MHz and use a single V
CC
of 1.7 V to 1.95 V that
makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered
power consumption.
S29NS-P MirrorBit
TM
Flash Family
S29NS512P S29NS256P S29NS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous
Read/Write, Multiplexed MirrorBit Flash Memory
Data Sheet
(Advance Information)
Read Access Times
Speed Option (MHz)
108
Max. Synch. Latency, ns (t
IACC
)
80
Max. Synch. Burst Access, ns (t
BACC
)
7.0
Max. Asynch. Access Time, ns (t
ACC
)
80
Max OE# Access Time, ns (t
OE
)
7.0
Current Consumption (typical values)
Continuous Burst Read @ 108 MHz
42 mA
Simultaneous Operation 108 MHz
60 mA
Program
30 mA
Standby Mode
20 μA
Typical Program & Erase Times
Single Word Programming
30 μs
Effective Write Buffer Programming (V
CC
) Per Word
6 μs
Effective Write Buffer Programming (V
PP
) Per Word
4 μs
Sector Erase (16 Kword Sector)
350 ms
Sector Erase (64 Kword Sector)
600 ms