參數(shù)資料
型號(hào)： S29NS512PABBJW003
廠商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： MirrorBit Flash Family
中文描述： 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁(yè)數(shù)： 51/86頁(yè)
文件大小： 2234K
代理商： S29NS512PABBJW003
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
51
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Software Functions and Sample Code
Note
Base = Base Address.
The following is a C source code example of using the reset function. Refer to the
Spansion Low Level Driver
User’s Guide
(
www.spansion.com
) for general information on Spansion Flash memory software development
guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is complete
The reset command may be written between the cycles in a program command sequence before
programming begins (prior to the third cycle). This resets the bank to which the system was writing to the
read mode.
If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the
Write to Buffer
Abort Reset
command sequence to RESET the device to reading array data. The standard RESET
command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command
sequence [see command table for details].
6.11
Programmable Output Slew Rate Control
This feature allows the user to change the output slew rate during a read operation by setting the
configuration register bit CR1.4. It allows 2 programmable slew rates. This feature is for users who do not
want to run the part at its maximum speed and could live with a slower output slew rate thereby reducing
noise variations at the output.
Table 6.28
Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Table 6.29
Programmable Output Slew Rate
Mode
Description
I
OL
& I
OH
1
Full Drive (Default)
100 μA
2
Half Drive
50 μA
相關(guān)PDF資料
PDF描述
S29NS-P MirrorBit Flash Family
S29PL127N65GFWW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL127N 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65GAWW02 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
S29PL129N65GAWW03 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
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