參數(shù)資料
型號： R5F562N8ADBG#U0
廠商： Renesas Electronics America
文件頁數(shù)： 92/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 176LFBGA
產品培訓模塊： RX Compare Match Timer
RX DMAC
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 126
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LFBGA
包裝： 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 46
2004 Microchip Technology Inc.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX20 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second word
of these instructions has the 4 MSBs set to ‘1’s and is
a special kind of NOP instruction. The lower 12 bits of
the second word contain data to be used by the instruc-
tion. If the first word of the instruction is executed, the
data in the second word is accessed. If the second
word of the instruction is executed by itself (first word
was skipped), it will execute as a NOP. This action is
necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
Set Summary” for further details of the instruction set.
EXAMPLE 4-3:
TWO-WORD INSTRUCTIONS
4.8
Look-up Tables
Look-up tables are implemented two ways. These are:
Computed GOTO
Table Reads
4.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF
PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Look-up table data may be stored 2 bytes per program
word by using table reads and writes. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
A description of the table read/table write operation is
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, execute 2-word instruction
1111 0100 0101 0110
; 2nd operand holds address of REG2
0010 0100 0000 0000
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes
1111 0100 0101 0110
; 2nd operand becomes NOP
0010 0100 0000 0000
ADDWF
REG3
; continue code
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