參數(shù)資料
型號(hào)： R5F562N8ADBG#U0
廠商： Renesas Electronics America
文件頁(yè)數(shù)： 46/148頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 176LFBGA
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 126
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LFBGA
包裝： 托盤(pán)
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PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 138
2004 Microchip Technology Inc.
12.3
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is
latched in interrupt
flag
bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 Interrupt Enable bit, TMR1IE
(PIE1<0>).
12.4
Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
12.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see
When
the
RD16
control
bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
12.6
Using Timer1 as a
Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
gives users the option to include RTC functionality to
their applications. This is accomplished with an inex-
pensive watch crystal to provide an accurate time base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to incre-
ment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it; the simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
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R5F562N8ADFB 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 144QFP 制造商:Renesas Electronics Corporation 功能描述:MCU,RX,32bit,100MHz,512KB Flash,LQFP144 制造商:Renesas Electronics Corporation 功能描述:MCU32Bit 165MIPS ROM512KRAM32K QFP144Pin
R5F562N8ADFB#V0 功能描述:MCU 32BIT FLASH 512KROM 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:RX600 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C，SPI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):11 程序存儲(chǔ)器容量:3.5KB（2K x 14） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 包裝:管件
R5F562N8ADFP 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 100QFP 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 100QFP 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 100QFP; Controller Family/Series:RX600; Core Size:32bit; No. of I/O's:72; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:100; Program Memory Size:512KB; RAM Memory ;RoHS Compliant: Yes 制造商:Renesas Electronics Corporation 功能描述:MCU32Bit 165MIPS ROM512KRAM32K QFP100Pin
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