參數(shù)資料
型號： PPC440GR-3BB533CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, BGA-456
文件頁數(shù)： 69/88頁
文件大?。?/td> 1177K
代理商： PPC440GR-3BB533CZ
AMCC Proprietary
71
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.19 – May 07, 2008
Figure 6. Input Setup and Hold Waveform
EMCRxClk input high time
35% of nominal period
–
ns
EMCRxClk input low time
35% of nominal period
–
ns
PerClk (and OPB Clock) output frequency (for ext. master or
sync. slaves)
33.33
66.66
MHz
PerClk period
15
30
ns
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
UARTSerClk input frequency
–
1000 / (2TOPB
1+2ns)
MHz
1
UARTSerClk period
2TOPB+2
–ns
1
UARTSerClk input high time
TOPB+1
–ns
1
UARTSerClk input low time
TOPB+1
–ns
1
TmrClk1 input frequency
–
100
MHz
2
TmrClk1 period
10
–
ns
TmrClk1 input high time
40% of nominal period
60% of nominal period
ns
TmrClk1 input low time
40% of nominal period
60% of nominal period
ns
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 66.66 MHz.
2. In RMII mode, 50MHz +/- 50PPM input EMCRefClk is required. In SMII mode, a 125 MHz +/- 100PPM input EMCRefClk is required.
Table 19. Peripheral Interface Clock Timings (Continued)
Parameter
Min
Max
Units
Notes
Clock
TIS
TIH
min
Inputs
Valid
1.25V
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