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參數(shù)資料
| 型號(hào)： | PPC440GR-3BB533CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-456 |
| 文件頁(yè)數(shù)： | 54/88頁(yè) |
| 文件大?。?/td> | 1177K |
| 代理商： | PPC440GR-3BB533CZ |
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58
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
NAND Flash Interface
NFALE
Address Latch Enable.
O
Multiplex
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
O
Multiplex
NFCLE
Command Latch Enable.
O
Multiplex
NFRdyBusy
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
I
Multiplex
NFREn
Read Enable strobe.
O
Multiplex
NFWEn
Write Enable strobe.
O
Multiplex
Serial Peripheral Interface
SCPClkOut
Clock output.
O
3.3V LVTTL
2
SCPDI
Data In.
I
3.3V LVTTL
2
SCPDO
Data output.
O
3.3V LVTTL
2
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
I/O
3.3V LVTTL
1
IRQ5
External interrupt request 5.
I
3.3V tolerant
2.5V CMOS
1
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
1
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-up
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
w/pull-up
1
TRST
Test Reset.
Note: Must be asserted low during a power-on system reset in
order to reset the JTAG interface. If the JTAG interface is not
reset, the processor may not boot.
I
3.3V LVTTL
w/pull-up
5
Table 9. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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