參數(shù)資料
型號: PPC440GR-3BB533CZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456
封裝: 35 X 35 MM, PLASTIC, BGA-456
文件頁數(shù): 61/88頁
文件大?。?/td> 1177K
代理商: PPC440GR-3BB533CZ
64
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Power Sequencing
Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete
(OVDD and VDD are below +0.4V) before a new power-up cycle is started.
Analog Voltage Filter
The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GR. A separate filter, as shown below, is recommended for each voltage.
The filter should keep the AVDD-AGNC (SAGND-SAGND) compression/expansion due to noise less than +50
mV.
All wire lengths of the filter circuit should be kept as short as possible to minimize coupling from other signals.
AGND (SAGND) must be connected to the digital ground plane at the AVDD (SAVDD) capacitor.
The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where noise is
expected.
Table 12. Overshoot and Undershoot
Receiver
AC Overshoot (V)
DC Overshoot (V)
DC Undershoot (V)
AC Undershoot (V)
TOS
3.3V LVTTL
3.9
3.6
0
-0.6
0.1*TCYC
1
2.5V (3.3V tolerant)
3.9
3.6
0
-0.6
0.1*TCYC
1
DDR
1.2*SOVDD
SOVDD + 0.3
0
-0.6
0.1/MemClkOut
PCI
1.2*OVDD
OVDD + 0.5
0
-0.2*OVDD
0.1/PCIClk
Notes:
1. TCYC is the period of the bus clock.
1/PerClk - EBC and NAND flash interfaces.
1/EMCRXClk - MII mode
1/EMCRefclk - RMII mode
1/SMIIRefClk - SMII mode
1/USB2Clk - UTMI
1/TrcClk - instruction trace interface
1/IIC0Clk and 1/IIC1Clk - IIC interfaces
1/SPIClkOut - SPI
L – SMT ferrite bead chip, Murata BLM21PG600SN1
C – 0.1
μF ceramic
VDD
AVDD, SAVDD
AGND, SAGND
GND
C
L
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