參數(shù)資料
型號： PPC440GR-3BB533CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, BGA-456
文件頁數(shù)： 48/88頁
文件大?。?/td> 1177K
代理商： PPC440GR-3BB533CZ
52
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Unused I/Os
Termination of unused receivers is generally required; however there are some exceptions that reduce or eliminate
the need for termination.
Signals Multiplexed with GPIO:
By Default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however is not needed if
the GPIO during initialization are configured as outputs. To configure as drivers, set and clear the appropriate bits in the
GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO chapter of the user’s manual.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0 [Gnt] signal low. Parking
forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The remaining PCI control signals must be
terminated as follows:
– Disable the internal PCI arbiter and enable PCI synchronous mode (See IIC Boot Strap Chapter in the user’s manual).
(Note: Synchronous mode is not supported when operating the PCI bus. This mode should only be used for
terminating an unused PCI interface).
– Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through
3kΩ resistors to +3.3v.
– Terminate PCIReq1:5 through
3kΩ resistors to +3.3v.
– Terminate PCIReq0[Gnt] through a
1kΩ resistor to GND.
DDR:
When ECC is not used, no termination is needed for unused ECC signals (ECC0:7, DM8, and DS8).
USB Host:
When the USB Host interface is not used, a clock is still required for USB1Clk in order to reset the USB Host. If the USB Host
does not reset, it can interfere with the internal PLB3 and OPB buses. The USB Host signals must be terminated as follows:
– A clock must be connected to USB1Clk. The clock can be any frequency from 32kHz to 48MHz.
– USB1HostXcvr and USB1HostXcv signals must be pulled down.
USB Device:
The USB Device requires a subset of the USB signals to be terminated.
– USB2LS0[Drvrlnh1][RejectPkt] must be pulled by unless used as a packet reject input.
– USB2D10:7, USB1DevXcvr, USB1DevXcvr and USB2Clk signals must be pulled down.
SMII0, RMII0 or MII:
– Configure EMAC0 to use internal clocks by setting SDR0_MFR[E0CS]=1 and reset EMAC0 by setting
EMAC0_MR0[SRST]=1.
– No pull ups or pull downs required
SMII1, RMII1 or MII:
– Configure EMAC1 to use internal clocks by setting SDR0_MFR[E1CS]=1 and reset EMAC1 by setting
EMAC0_MR1[SRST]=1.
– No pull ups or downs required.
Oddities:
TmrClk2 must be connected to a clock to ensure reset of internal logic. It can be connected to any available clocks
in the frequency range of 32kHz to 100MHz.
相關(guān)PDF資料
PDF描述
PPC440GRX-STA400TZ 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680
PPCM08DNNNN920 8 CONTACT(S), PLASTIC, MALE, CIRCULAR CONNECTOR, CRIMP, PLUG
PRAF06ANNNN91502 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
PRAF06ANNNN915 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
PRAF08ANNNN91502 8 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
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