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參數(shù)資料
| 型號(hào)： | PPC440GR-3BB533CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-456 |
| 文件頁(yè)數(shù)： | 57/88頁(yè) |
| 文件大小： | 1177K |
| 代理商： | PPC440GR-3BB533CZ |
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60
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Trace Interface
TrcBS0:2
Trace branch execution status.
I/O
3.3V tolerant
2.5V CMOS
TrcClk
Trace data capture clock, runs at 1/4 the frequency of the
processor.
O
3.3V tolerant
2.5V CMOSL
TrcES0:4
Trace Execution Status is presented every fourth processor
clock cycle.
I/O
3.3V LVTTL
TrcTS0:6
Additional information on trace execution and branch status.
I/O
3.3V tolerant
2.5V CMOS
Power
VDD
1.5V supply—Logic voltage.
na
OVDD
3.3V supply—I/O (except DDR SDRAM, Ethernet).
na
SVDD
2.5V supply—SDRAM, Ethernet.
na
GND
Ground.
na
AVDD
1.5V—Filtered voltage for system PLLs (analog).
na
AGND
PLL (analog) voltage ground.
na
SAVDD
1.5V—Filtered voltage for memory PLL (analog).
na
SAGND
PLL (analog) memory voltage ground.
na
Other
Reserved
To avoid noise pickup problems, most of these balls must be
connected in the board design as shown Table 8 on page 51.
na
Table 9. Signal Functional Description (Sheet 8 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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