參數(shù)資料
型號(hào)： PPC440GR-3BB533CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, BGA-456
文件頁數(shù)： 46/88頁
文件大?。?/td> 1177K
代理商： PPC440GR-3BB533CZ
50
AMCC Proprietary
Revision 1.19 – May 07, 2008
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Signal Descriptions
The PPC440GR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The
following tables describe the package level pinout.
In the table “Signal Functional Description” on page 53, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Alphabetically” on page 19 for the pin (ball) number to which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals
Listed Alphabetically” on page 19. It is expected that in any single application a particular pin will always be
programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin
selection than would otherwise be possible. The circuit type for multiplexed signals is shown as “Multiplex.” The
actual circuit type is the same as the primary signal.
Note: Signals multiplexed wit GPIO default to GPIO receivers and float after reset. Initialization software must
configure the GPIO registers for the desired function as described in the GPIO chapter of the User’s Manual. Any
of these signals requiring a particular state prior to running initialization code must be terminated with pull ups or
pull downs.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440GR to broadcast an address to external slave devices when the
PPC440GR has control of the external bus. When during the course of normal chip operation an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC440GR. In this example, the pins are also bidirectional, serving both as inputs
Table 7. Pin Summary
Group
No. of Pins
Signal pins, non-multiplexed
221
Signal pins, multiplexed
62
Total Signal Pins
283
AVDD
1
SAVDD
1
SAGnd
1
AGnd
1
OVDD
18
SVDD
18
VDD
32
Gnd
80
Total Power Pins
152
Reserved
21
Total Pins
456
相關(guān)PDF資料
PDF描述
PPC440GRX-STA400TZ 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680
PPCM08DNNNN920 8 CONTACT(S), PLASTIC, MALE, CIRCULAR CONNECTOR, CRIMP, PLUG
PRAF06ANNNN91502 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
PRAF06ANNNN915 6 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
PRAF08ANNNN91502 8 CONTACT(S), ALUMINUM ALLOY/COPPER ALLOY/COPPER-ZINC ALLOY, CIRCULAR CONNECTOR, CRIMP
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