- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383724 > ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver PDF資料下載
參數(shù)資料
| 型號： | ORT8850L |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 71/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
Agere Systems Inc.
71
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Table 31. Embedded Core/FPGA Interface Signal Description
(continued)
Pin Name
I/O
Description
STM or 8B/10B Signals
(continued)
doutac<7:0>
doutac_par
doutac_spe
doutac_c1j1
doutac_en
doutac_fp
doutad<7:0>
doutad_par
doutad_spe
doutad_c1j1
doutad_en
doutad_fp
doutba<7:0>
doutba_par
doutba_spe
doutba_c1j1
doutba_en
doutba_fp
doutbb<7:0>
doutbb_par
doutbb_spe
doutbb_c1j1
doutbb_en
doutbb_fp
doutbc<7:0>
doutbc_par
doutbc_spe
doutbc_c1j1
doutbc_en
doutbc_fp
doutbd<7:0>
doutbd_par
doutbd_spe
doutbd_c1j1
doutbd_en
doutbd_fp
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Parallel bus of STM slice A, receiver C. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver C.
SPE signal for parallel bus of STM slice A, receiver C.
C1J1 signal for parallel bus of STM slice A, receiver C.
Enable for parallel bus of STM slice A, receiver C.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver C.
Parallel bus of STM slice A, receiver D. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver D.
SPE signal for parallel bus of STM slice A, receiver D.
C1J1 signal for parallel bus of STM slice A, receiver D.
Enable for parallel bus of STM slice A, receiver D.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver D.
Parallel bus of STM slice B, receiver A. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver A.
SPE signal for parallel bus of STM slice B, receiver A.
C1J1 signal for parallel bus of STM slice B, receiver A.
Enable for parallel bus of STM slice B, receiver A.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver A.
Parallel bus of STM slice B, receiver B. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver B.
SPE signal for parallel bus of STM slice B, receiver B.
C1J1 signal for parallel bus of STM slice B, receiver B.
Enable for parallel bus of STM slice B, receiver B.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver B.
Parallel bus of STM slice B, receiver C. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver C.
SPE signal for parallel bus of STM slice B, receiver C.
C1J1 signal for parallel bus of STM slice B, receiver C.
Enable for parallel bus of STM slice B, receiver C.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver C.
Parallel bus of STM slice B, receiver D. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver D.
SPE signal for parallel bus of STM slice B, receiver D.
C1J1 signal for parallel bus of STM slice B, receiver D.
Enable for parallel bus of STM slice B, receiver D.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver D.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OS1001 | Interface IC |
| OS1010 | Optoelectronic |
| OS1011 | SINGLE 1.8V, 200 KHZ OP, E TEMP, -40C to +125C, 8-PDIP, TUBE |
| OS1012 | 1.8V, 200kHz single low-cost, CMOS Op Amplifier on 120K Analog ROM process., -40C to +125C, 8-MSOP, T/R |
| OS1013 | 1.8V, 200kHz single low-cost, CMOS Op Amplifier on 120K Analog ROM proccess., -40C to +125C, 5-SOT-23, T/R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850L-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850L-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。