參數(shù)資料
型號： ORT8850L
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 33/112頁
文件大?。?/td> 2417K
代理商： ORT8850L
Agere Systems Inc.
33
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Backplane Transceiver Core Detailed
Description
(continued)
Receive Bypass Options and FPGA Interface
Not all of the blocks in the receive direction are
required to be used. The following bypass options are
valid in the receive (backplane
→
FPGA) direction:
I
STM Pointer Mover bypass:
—
In this mode, data from the alignment FIFOs is
transferred to the FPGA logic. All channels are
synchronous to the fpga_sysclk signals driven to
the FPGA logic, as is also the case when the
pointer mover is not bypassed. During bypass
SPE, C1J1, and data parity signals are not valid.
When the pointer mover is bypassed, a frame
pulse from aligned channels (doutxy_fp) is pro-
vided by the embedded core. When the pointer
mover is used, the FPGA logic provides the frame
pulse on the line_fp signal.
I
STM Pointer Mover and Alignment FIFO bypass:
—
In this mode, data from the framer block is
transferred to the FPGA logic. All channels supply
data and frame pulses synchronous with their
individual recovered clock (cdr_clk_xy) per
channel. During bypass, SPE, C1J1, and data
parity signals are not valid.
I
8B/10B Alignment FIFO bypass:
—
When in 8B/10B mode, the data from the 8B/10B
decoder is passed to the FPGA logic if the align-
ment FIFO is bypassed. All channels suppply data
and COMMADET signals synchronous with their
individual recovered clock (cdr_clk_xy) per chan-
nel. When not bypassed, the 8B/10B alignment
clock provides all channels and a COMMADET
signal synchronous to the fpga_sysclk signal to
the FPGA logic.
Powerdown Mode
Powerdown mode will be entered when the corre-
sponding channel is disabled. Channels can be inde-
pendently enabled or disabled under software control.
Parallel data bus output enable and TOH serial data
output enable signals are made available to the FPGA
logic. The HSI macrocell
’
s corresponding channel is
also powered down. The device will power up with all
eight channels in powerdown mode.
STM Redundancy and Protection Switching
The ORT8850 supports STS-12/STS-48 redundancy
by either software or hardware control for protection
switching applications. For the transmitter mode, no
additional functionality is required for redundant opera-
tion. For receiving data, STS-12 and STS-48 data
redundancy can be implemented within the same
device, while STS-192 and above data stream requires
multiple ORT8850 devices to support redundancy.
In STS-12 mode, the channel A receive data bus port is
used for both channel A and channel B. Similarly, the
channel C receive data bus port is used for both chan-
nel C and channel D. Channel B and channel D
become the redundant channels. The channel B and
channel D receive data bus ports are unused. Soft reg-
isters provide independent control to the protection
switching MUXes for both parallel data ports and serial
TOH data ports. When direct hardware control for pro-
tection switching is needed, external protection switch
pins are available for channels A and B, and also chan-
nels C and D. The external protection switch pins only
support parallel SPE/TOH data protection switching,
but not the serial TOH data. these protection switching
pins are listed in Table 28 as prot_switch_xx.
For STS-48 redundancy, the two 4-channel macro
blocks are both used: four channels for work and four
channels for protect. The switching between work and
protect is extended to either be between four-channel
macros or between the A/B and C/D channels within
both macros.
In STS-192 mode, multiple independent devices are
required to work and protect for redundancy. Parallel
and serial port output pins on the FPGA side should be
3-stated as the basis for supporting redundancy. The
existing local bus enable signals at the CIC can be
used as 3-state controls for FPGA data bus if needed,
which can be easily accessed by software control.
Users can also create their own protection switch
3-state enable signals either in FPGA logic or external
to the device, depending on the specific application.
The STM protection switch circuitry is not available in
8B/10B mode or STM pointer mover and alignment
FIFO bypass mode. It is available when only the
pointer mover is bypassed.
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